Track 01 · SystemVerilog Primer

Vectors, Arrays, and Bit Widths

~12 min Hands-on lab 1 exercise Verilator
Page 04 of 20
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01
Multi-Bit Vectors

Most real signals are not a single bit. A vector is a signal that holds several bits at once, and you declare its width with a range, written as a high index down to a low index. A signal that holds eight bits, for example, spans index seven down to index zero. The width you choose is a promise about how many bits the signal can carry.

This is different from what you declared in Page 03, where each signal was a single bit. Vectors are how you represent buses, register values, addresses, and data paths — everything that carries more than one bit at a time. The rest of this page is about keeping the width promise you make when you declare one.

02
Packed Versus Unpacked Arrays

There are two ways to group bits. A packed array is a contiguous block of bits you can treat as a single number, which is what you want for buses and anything you do arithmetic on. An unpacked array is a collection of separate elements, which is what you want for things like a memory or a list, where each element stands on its own.

The distinction matters because a packed array behaves like a wide integer — you can slice it, assign a number to it, compare it directly. An unpacked array behaves like a list of separate signals. Use packed when the thing is one value. Use unpacked when it is many. In this lab and in most bus-level verification work, you will be working with packed vectors.

03
Indexing and Slicing

Once a signal holds several bits, you often want only some of them. Indexing picks a single bit by its position. Slicing picks a range of bits, written as a high index down to a low index, and gives you back a smaller vector. In an eight-bit signal declared [7:0], bit seven is the most significant bit and bit zero is the least significant.

Getting the indices right is the difference between reading the field you meant and reading the wrong bits entirely. An off-by-one on a slice range shifts every bit you read by one position. The result compiles cleanly, runs without error, and produces wrong data. The only defence is counting carefully.

04
Key Insight — The Silent Truncation

Here is the trap, and it is one of the most common bugs in real designs. If you assign a wide value to a signal that is too narrow, the extra top bits are silently dropped. Nothing errors. The value is simply wrong from that point on.

The most common form is an off-by-one width: a signal declared one bit too narrow, or a slice range off by a single index. These mistakes hide precisely because they do not crash. The discipline that prevents them is simple: count the bits you need, declare exactly that many, and check your slice ranges. This lab makes a width mistake visible so you learn to catch it before it costs you.

Why this matters in real designs

A narrowly declared address bus in a register file quietly drops the top address bits. Every access lands on the wrong register. The simulation compiles, the waveform looks busy, and the bug ships. Width hygiene is not a detail. It is structural correctness.

Lab Exercise
Lab — Declare the Widths and Write the Slice

Declare each signal below with the correct width, then complete the slice so it extracts the top four bits. Run and submit. The test drives a full-width value through your declarations and checks that no bits were lost.

Grading method: structural check — the checker parses your declared widths and your slice expression. A signal declared too narrow causes a truncation failure with the exact dropped bits shown.
Checking widths and slice…
Pass
Correct. Your widths held the full value and your slice picked the right bits. Nothing was truncated.
Truncation — Bits Were Lost
Your code compiled, but bits were lost. A signal was declared too narrow, so the top bits of the value were silently dropped. The engine output and the AI mentor below show where the truncation occurred.
Engine output
AI Mentor
Compile Error
The checker found a syntax issue before evaluating your widths. Resolve the error below and resubmit.
Checker output
AI Mentor
Engine Error
Something went wrong on our end. Please try submitting again in a moment.
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