Jobs Archive
Browse 3 months of semiconductor & AI roles • Sort by date, experience, or package • 20 jobs per page
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Emulation Engineer — AI Accelerator Verification (EnCharge AI)
Verification
Emulation AI Accelerator Architecture Verification Tape-out
SoC Machine Learning Design Engineer (Apple)
AI Silicon
SoC Design Machine Learning Accelerators RTL Architecture
FPGA & Signal Processing Engineer (Anmaya Technologies)
FPGA
FPGA Verilog VHDL Digital Signal Processing
Silicon Photonics Modeling Engineer — Photonic Device & PIC Design (Best NanoTech)
Photonics
Silicon Photonics PIC Design Photonic Device Modeling
Sr. Staff / Staff Board Package Design Engineer (Renesas Electronics)
Packaging
IC Packaging Substrate Design Power Distribution Signal Integrity
Signoff Methodology Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyEDA Tools
Static Timing Analysis Signoff EDA Tools Multi-physics Scripting
Associate Analyst, Applications Programming (Analog Devices)
✅ Fresher FriendlySoC Architecture
Applications Programming Embedded Systems C Debugging
Senior VLSI Design Engineer — IO Design, High Speed DDR (SanDisk)
RTL Design
Analog/Mixed Signal Design IO Circuits DDR Custom Digital
Principal Hardware DFT Lead (NXP Semiconductors)
DFT
DFT Architecture Scan Insertion ATPG BIST Test Engineering
ASIC Floorplan Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Floorplanning ASIC Design VLSI Timing Closure Python
CPU CAD Engineer (Qualcomm)
EDA Tools
CAD Flow Development EDA Tools Synthesis STA Scripting (Perl/Python/TCL)
AI EDA Applications Engineer (Best NanoTech)
AI Silicon
EDA Tools DFT Signoff AI-driven Design Automation Synthesis
Senior Staff VLSI Design Engineer — SystemC, Functional Modeling, Verification (Sandisk)
Verification
SystemC C++ Functional Modeling Verification NAND Memory
Hardware Engineer — FPGA Design Techniques (Happiest Minds Technologies)
✅ Fresher FriendlyFPGA
FPGA Design Verilog/VHDL Xilinx/Altera Tools Digital Logic
Lead Photonic IC Design Engineer (Seer)
Photonics
Photonic IC Design Optical Waveguides PIC Simulation Optical Switches
Digital Design Engineer — RTL/ASIC, AI Accelerators (Mentium Technologies)
RTL Design
RTL Design SystemVerilog ASIC Front-end EDA Tools AI Accelerator Architecture
SOC AI Power and Performance Validation — Undergrad Intern (Intel)
✅ Fresher FriendlySoC Architecture
SoC Validation Power Analysis Performance Analysis CPU/SoC Architecture Python
ASIC Physical Design Engineer, Netlisting — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Netlisting RTL Physical Design Synthesis Perl/Python ASIC Flow
DFT Architect (Mulya Technologies)
DFT
DFT Architecture Scan ATPG BIST JTAG Boundary Scan
Director, Front-end SoC Design (AMD)
SoC Architecture
SoC Design GPU Architecture RTL Team Leadership Instinct GPU
Factory Applications Engineer — Silicon Photonics (Teradyne)
Photonics
Silicon Photonics Optical Test PIC Characterization Applications Engineering
Application Engineer — EDA Rotational Program (Cadence)
✅ Fresher FriendlyEDA Tools
EDA Tools Customer Support Silicon Design Automation Tcl Python
Senior Engineer, Semiconductor Packaging (Analog Devices)
Packaging
IC Packaging Reliability Engineering Package Materials Manufacturing
SoC Performance Modeling & Architecture Engineer (AMD)
SoC Architecture
SoC Architecture Performance Modeling Microarchitecture Workload Analysis
ASIC Design Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM RTL Verification Functional Coverage Python
Digital Physical Design Engineer (NXP Semiconductors)
Physical Design
Synthesis Place & Route Static Timing Analysis ECO EDA Tools
Senior DFT ATPG Engineer (NVIDIA)
DFT
DFT ATPG Scan Insertion Post-Silicon Validation DFX
ASIC Clocks Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
RTL Design Verilog Clock Distribution ASIC Design Flow
AI Silicon, Junior Digital Design Engineer (Unconventional AI)
✅ Fresher FriendlyAI Silicon
SoC Design Digital Design Neural Network Hardware Mapping Verilog
FPGA Design Engineer III (Kopin Corporation)
FPGA
FPGA Design High-Speed Digital Interfaces Embedded Processors VHDL/Verilog
Advanced Photonics Engineer (GlobalFoundries)
Photonics
Silicon Photonics PIC Design Process Integration Optical Testing
Physical Design Methodology and Operations Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Physical Design EDA Tools Scripting (Python/TCL) Floorplanning Place & Route
Senior Physical Design Engineer (LeadIC Design)
Physical Design
Floorplanning Placement CTS Routing STA Synopsys ICC2 PrimeTime
ASIC/SoC Design Verification Engineer (Sivaltech)
Verification
SystemVerilog UVM Verification Planning Coverage Assertions
UCIe Application Engineer, Sr Staff (Synopsys)
EDA Tools
UCIe Die-to-Die Interconnect IP Integration SerDes EDA Tools
Hardware System Validation Engineer (Apple)
DFT
Silicon Validation DFT ATE Debug System-level Testing
Senior ASIC Design Engineer — Agentic AI (NVIDIA)
AI Silicon
ASIC Design Flow RTL GPU Architecture Agentic AI Python
Mac Hardware Systems Engineer (SoC) (Apple)
SoC Architecture
SoC Architecture System Integration Power Analysis Board Bring-up
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
RTL Design Verilog ASIC Design Flow Logic Synthesis Timing Analysis
Silicon Engineer, Platform and Devices — University Graduate 2026 (Google)
✅ Fresher FriendlyRTL Design
Digital Design Verilog SoC Circuit Design Silicon Bring-up
Lead DFT Engineer (NXP Semiconductors)
DFT
Scan Insertion ATPG GLS DFT Architecture
Interim Engineering Intern_2027_HW (Qualcomm)
✅ Fresher FriendlyAI Silicon
Digital Design SoC Fundamentals Verilog Computer Architecture
2027 Campus Hire — Associate Engineer, HW (Qualcomm)
✅ Fresher FriendlySoC Architecture
SoC Verification RISC/DSP Processors Digital Design
Lead Silicon Photonics Engineer (Neurophos)
Photonics
Silicon Photonics Electromagnetic Simulation PIC Design
Intern — Design Validation (Silicon Labs)
✅ Fresher FriendlyVerification
Design Validation Digital Design Verification Basics Lab Debug
Senior ASIC Design Engineer — DFX (NVIDIA)
Physical Design
SoC Architecture RTL Design Verilog Microarchitecture DFX
Mixed Signal Logic Design Engineer (Intel)
RTL Design
RTL Design Mixed-Signal Design Low Power Design Verilog
RTL Design — Sr Engineer (Qualcomm)
RTL Design
RTL Design Verilog Microarchitecture Low Power Design
Hardware System Engineer — iPhone System Technology, SoC (Apple)
SoC Architecture
SoC Architecture EE Fundamentals System Validation Hardware Debug
Staff VLSI Design Engineer — Verification, NAND Memory (SanDisk)
Verification
SystemVerilog UVM Functional Verification NAND Memory
MTS Packaging Engineer (AMD)
Packaging
Advanced Packaging 2.5D/3D IC Package Design Automation
Principal ASIC Chip Design Engineer — SoC Architecture (NVIDIA)
SoC Architecture
SoC Architecture ASIC Design Microarchitecture RTL
ASIC Design Engineer, BOOT and Power Management — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
RTL Design Verilog SystemVerilog Power Management Boot Sequences
Early Careers SoC Physical Design Engineer (m/f/d) (Apple)
✅ Fresher FriendlyPhysical Design
Physical Design Place & Route STA Synthesis SoC
DFT Engineer (Weekday AI)
DFT
DFT ATPG Scan Insertion RTL Fault Modeling
Formal Verification Lead — AI Accelerator Silicon (Tesla)
Verification
Formal Verification SystemVerilog JasperGold AI Accelerator
AI/ML Hardware Architect, Cloud, Silicon (Google)
AI Silicon
Computer Architecture AI/ML Hardware ASIC Silicon
Engineer — FPGA Design (Fresher) (Tejas Networks)
✅ Fresher FriendlyFPGA
FPGA VHDL Verilog Digital Design
Silicon Photonics Development Engineer (Chromopic)
Photonics
Silicon Photonics Optics PIC Design Applied Physics
Applications Engineering, Principal Engineer — Synthesis & P&R (Synopsys)
EDA Tools
Synthesis Place & Route EDA Tools ASIC Implementation
Analog Circuit Design Engineer — Graduate Intern (Intel)
✅ Fresher FriendlyAnalog Design
Analog Circuit Design SPICE Mixed-Signal Design Cadence Virtuoso
ASIC Physical Design Apprenticeship — 12-Month Program (Synopsys)
✅ Fresher FriendlyPhysical Design
Physical Design DFT Signal Integrity Analysis EDA Tools
Advanced Package Design Engineer (AMD)
Packaging
2.5D/3D Packaging IC Packaging Vendor Ecosystem Yield Analysis
Lead Silicon Photonics Design Engineer (Coherent Corp)
Photonics
Silicon Photonics PIC Design Optical Devices Photonic Circuit Simulation
ASIC Engineer, Architecture — AI Accelerator Silicon (Meta)
AI Silicon
AI Accelerator Architecture ASIC Design ML Hardware Performance Modeling
Senior Design Verification Engineer (Eximietas Design)
Verification
SystemVerilog UVM Design Verification Testbench Development
Senior ASIC Design Engineer — RTL & Microarchitecture (NVIDIA)
RTL Design
RTL Design Verilog Microarchitecture Synthesis Timing Analysis
Senior ASIC Hardware Design Engineer — CPU/SoC (NVIDIA)
SoC Architecture
SoC Architecture Micro-architecture RTL Development CPU Design Verilog
ASIC Design Efficiency Engineer (NVIDIA)
EDA Tools
EDA Tools Design Flow Automation Scripting Python TCL
VLSI Physical Design Engineer — Fresher/Junior (Vtricks Technologies)
✅ Fresher FriendlyPhysical Design
Physical Design Floorplanning Placement & Routing Advanced Nodes (7nm/5nm)
Technical Internship 2026 — Fresher Opportunity (NXP Semiconductors)
✅ Fresher FriendlyPackaging
VLSI Fundamentals Embedded Systems Semiconductor Basics Digital Design
ASIC Physical Design Engineer — RTL to GDSII (NVIDIA)
Physical Design
Physical Design Synthesis Place & Route Formal Verification
CPU Emulation Engineer, Multiple Levels (Qualcomm)
Verification
Emulation Palladium Zebu CPU Verification
SoC QoS/Fabric Performance Engineer, Platform Architecture (Apple)
SoC Architecture
SoC Architecture Performance Modeling Interconnect C++
VLSI Design Verification & RISC-V Trainer (Nation Innovation)
✅ Fresher FriendlyVerification
RISC-V UVM SystemVerilog Training
ASIC Design Engineer — High Speed IO (NVIDIA)
SoC Architecture
RTL High Speed IO Micro-architecture Verilog
Senior DFT Design Engineer — ATPG/Scan Stitching (AMD)
DFT
ATPG Scan Insertion DFT Tetramax
Staff Digital Engineer — DFT Design (Renesas Electronics)
DFT
DFT ATPG Scan Digital Design
ASIC Verification Engineer — Hyderabad (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM ASIC Verification RTL
ASIC Design Engineer, Clocks (NVIDIA)
RTL Design
RTL Clock Design Verilog STA
ASIC Design Engineer — RTL & Microarchitecture (NVIDIA)
RTL Design
RTL Design Microarchitecture SystemVerilog Verilog Performance Analysis
Internship, AI Hardware Silicon Validation Engineer — Fall 2026 (Tesla)
✅ Fresher FriendlyAI Silicon
Silicon Validation Post-Silicon Bring-up Lab Equipment Python AI Hardware
Associate ASIC and/or FPGA Design and Verification Engineer (Boeing)
✅ Fresher FriendlyFPGA
VHDL Verilog FPGA Design ASIC Verification Digital Logic
Photonics Process Development Engineer 2 — Packaging & Tooling (Monarch Quantum)
Photonics
Silicon Photonics PIC Packaging Process Development Optical Alignment Cleanroom
Functional Verification Applications Engineer (Siemens EDA)
EDA Tools
QuestaSim Functional Verification EDA Tools Customer Design Flows SystemVerilog
Tapeout Engineer — 2026 New College Graduate (GlobalFoundries)
✅ Fresher FriendlyPackaging
Tapeout Mask Data Prep Data Engineering Cloud Architecture Analytics
SoC Architecture Engineer — High-Speed Automotive SerDes SoCs (Texas Instruments)
SoC Architecture
SoC Architecture SerDes High-Speed Interfaces System-Level Design Automotive
Mixed Signal Design Verification Engineer (Intel)
Verification
Analog/Mixed-Signal Verification SPICE Circuit Simulation Floorplanning Chip Extraction
ASIC Floorplan Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Floorplanning Physical Design Timing Closure Place & Route Python
DFT Design Engineer (Intel)
DFT
Scan Insertion ATPG DFT Architecture GLS Boundary Scan
RFIC Digital Verification Engineer (Qualcomm)
Verification
RFIC Digital Verification SystemVerilog UVM Mixed-Signal
Senior Physical Design Engineer (HCLTech)
Physical Design
Place & Route STA Synthesis Floorplanning ICC2/Innovus
ASIC Physical Design Engineer, Netlisting — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Netlisting Physical Design ASIC Flow Timing Analysis Scripting
ASIC Design Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM RTL Verification Simulation Debug
DFT Engineer — Tile & SoC-Level ATPG (AMD)
DFT
ATPG Scan Insertion Pattern Retargeting DFT Architecture Tetramax
SoC Physical Design Engineer — Power Delivery (Apple)
Physical Design
ASIC Integration Power Delivery Floorplanning Clock & Power Networks
Sr. Principal SoC Architect — AI Accelerator Silicon (SiMa.ai)
AI Silicon
SoC Architecture AI Accelerators System-Level Integration Silicon-Software Co-design
FPGA Developer Internship (Vicharak Computers)
✅ Fresher FriendlyFPGA
Verilog VHDL FPGA Prototyping Embedded Systems HDL
Silicon Photonics Senior Design Engineer (Cisco)
Photonics
Silicon Photonics PIC Design Optical Engineering Packaging
Principal Engineer, VLSI Design Verification — NAND Memory (SanDisk)
Verification
SystemVerilog UVM NAND Memory Verification Methodology Formal Verification
Silicon Photonics PIC Design Engineer (Broadcom)
Photonics
Silicon Photonics PIC Design Optical Interconnects Simulation Tools
Software Engineer, Associate — QuestaSim R&D (Siemens EDA)
✅ Fresher FriendlyEDA Tools
C++ Simulation Algorithms Verilog/VHDL Software Development
Packaging Engineer — Semiconductor Equipment (Applied Materials)
Packaging
IC Packaging Advanced Packaging Reliability Testing Materials Science
Principal Architect, AI and Semiconductors (Google)
SoC Architecture
SoC Architecture AI Accelerators System Design Cloud Infrastructure
Design Engineer, Verification — 2026 New College Graduate (GlobalFoundries)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verilog Digital Logic Design Python
Physical Design Intern (SK hynix)
✅ Fresher FriendlyPhysical Design
Physical Design Synthesis Place & Route STA VLSI Fundamentals
Lead DFT Engineer (NXP Semiconductors)
DFT
Scan Insertion ATPG MBIST GLS DFT Architecture
HW Design Intern — Logic Design & Verification (Lattice Semiconductor)
✅ Fresher FriendlyRTL Design
Verilog Logic Design RTL Verification Physical Design Basics
Senior NPU Architect — AI Accelerator Silicon (EnCharge AI)
AI Silicon
NPU Architecture AI Accelerators Microarchitecture Compute-in-Memory C++
Senior FPGA Engineer — Signal Processing (Dhruva Space)
FPGA
FPGA VHDL Verilog Signal Processing Xilinx Vivado
ASIC Physical Design Engineer, Netlisting — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Physical Design Netlisting Place & Route Floorplanning Timing Closure
Senior Package Layout Engineer, Hardware (NVIDIA)
Packaging
IC Package Design Layout Signal Integrity Power Integrity
Mac Hardware Systems Engineer — SoC (Apple)
SoC Architecture
SoC Architecture System Integration Power Analysis Hardware Bring-up
EDA Tool Developer (AMD)
EDA Tools
C++ Python EDA Tool Development Algorithms Scripting
Senior Principal Engineer, Analog Design — HBM PHY (Marvell Technology)
AI Silicon
Analog IC Design HBM PHY SERDES Mixed-Signal Circuit Design
DFX Verification Engineer (Tessolve)
Verification
DFT Scan ATPG BIST Verification
Staff Analog Design Engineer — Photonic Computing (IC Resources)
Photonics
Analog IC Design Photonic Computing Mixed-Signal Circuit Design
FPGA Software Engineer — Entry Level (Zoppler Systems)
✅ Fresher FriendlyFPGA
FPGA VHDL Verilog Embedded Systems Digital Design
DFT Engineer — Memory BIST & Scan (NVIDIA)
DFT
Scan Insertion ATPG JTAG MBIST DFT Compiler
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design Digital Logic ASIC Flow
Performance Modeling Engineer — Data Center SoC (AMD)
SoC Architecture
Performance Modeling C++ Python Computer Architecture SoC Analysis
Design Verification Engineer (Cadence)
EDA Tools
SystemVerilog UVM Functional Verification Debug Test Environment Development
SOC Engineering — Principal Engineer, DFT (Synopsys)
DFT
DFT ATPG Scan Insertion BIST SoC Test Architecture
RTL — FPGA Design Engineer (ACL Digital)
FPGA
Verilog VHDL Xilinx FPGA Verification Timing Closure
ASIC Hardware Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog RTL Design Microarchitecture Digital Logic Design Computer Architecture
2026 Campus Hire — Associate Engineer, HW (Qualcomm)
✅ Fresher FriendlySoC Architecture
Digital Design VLSI Fundamentals Verilog Computer Architecture Embedded Systems
Engineer / Associate Engineer — AI Platform (Qualcomm)
✅ Fresher FriendlyAI Silicon
Python C++ Machine Learning AI Accelerators Linux
Formal Verification Engineer — Silicon Chassis (Intel)
Verification
Formal Verification SystemVerilog JasperGold Model Checking Assertions
Physical Design Engineer — Client/Server ASIC Hard-IP (Intel)
Physical Design
Place and Route STA Physical Verification Synthesis Analog Layout
DDR Lead Verification Engineer — Memory Controller IP (AMD)
Verification
SystemVerilog UVM DDR/Memory Controller Formal Verification Coverage Closure
Principle DFT Engineer (NXP Semiconductors)
DFT
DFT Scan Insertion ATPG Gate-Level Simulation
Engineer — RF SW, Modem-RF Wireless (Qualcomm)
✅ Fresher FriendlySoC Architecture
RF Systems Digital Communications Embedded SW Modem
RTL Design — Staff Engineer (Qualcomm)
RTL Design
RTL Design Verilog Microarchitecture Low Power Design
Early Careers SoC Physical Design Engineer (Apple)
✅ Fresher FriendlyPhysical Design
Physical Design Clock Network Design Place and Route STA
SoC Physical Design Engineer — Electrical Analysis (Apple)
Physical Design
ASIC Physical Implementation Electrical Analysis Scripting Verification Flows
ASIC Design Engineer — BOOT and Power Management (NVIDIA)
RTL Design
RTL Design Verilog Power Management Boot ROM Low Power Design
Senior Cell Modeling and Verification Engineer (NVIDIA)
Verification
Cell Characterization Liberty Modeling SPICE Hardware Verification
Formal Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
Formal Verification SystemVerilog Assertions GPU Architecture
FPGA Prototyping and Emulation Engineer (NVIDIA)
FPGA
FPGA Prototyping Emulation HAPS Palladium SoC Bring-up
DFT Engineer — ATPG/Scan Insertion (AMD)
DFT
DFT ATPG Scan Insertion GLS Tetramax
GPU Design Verification Sr Lead Engineer (Qualcomm)
Verification
GPU Verification UVM RTL Debug Simulation Infrastructure
Mixed-Signal IP Verification Engineer (Intel)
Verification
Memory PHY Mixed-Signal Verification Pre-Silicon DV
Verification CAD Engineer — Sr Staff (Qualcomm)
Verification
DV Methodologies UVM Testbench Python Verification Infrastructure
ASIC Verification Engineer — 0–2 Years Fresher (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM C/C++ RTL Simulation Basic Verification
Physical Design Trainee — Fresh Grad (Quest Global)
✅ Fresher FriendlyPhysical Design
Synopsys Tools Physical Design Fundamentals VLSI Basics
Applied ML Engineer — Circuit Design (NVIDIA)
✅ Fresher FriendlyAI Silicon
Machine Learning Circuit Design Python AI/ML Fundamentals
Senior Verification Engineer — ARM Fabric Unit (NVIDIA)
Verification
SystemVerilog UVM ARM Architecture Formal Verification Python
Design Verification Engineer — PCIe/CXL Protocol (RTLYNX)
Verification
PCIe CXL Protocol UVM SystemVerilog VIP Integration
Pre-Si Verification Engineer — SoC Frontend (Intel)
Verification
SoC Verification RTL Debug Simulation Formal Methods
ASIC Physical Design Engineer — XBAR IP (NVIDIA)
Physical Design
RTL to GDSII Synthesis Place & Route Timing Analysis
Design Verification Engineer — PCIe/CXL Protocol (RTLYNX)
Verification
PCIe CXL Protocol UVM SystemVerilog VIP Integration
Pre-Si Verification Engineer — SoC Frontend (Intel)
Verification
SoC Verification RTL Debug Simulation Formal Methods
ASIC Physical Design Engineer — XBAR IP (NVIDIA)
Physical Design
RTL to GDSII Synthesis Place & Route Timing Analysis
GPU Design Verification Sr Lead Engineer (Qualcomm)
Verification
GPU Verification UVM RTL Debug Simulation Infrastructure
Mixed-Signal IP Verification Engineer (Intel)
Verification
Memory PHY Mixed-Signal Verification Pre-Silicon DV
Verification CAD Engineer — Sr Staff (Qualcomm)
Verification
DV Methodologies UVM Testbench Python Verification Infrastructure
ASIC Verification Engineer — 0–2 Years Fresher (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM C/C++ RTL Simulation Basic Verification
Physical Design Trainee — Fresh Grad (Quest Global)
✅ Fresher FriendlyPhysical Design
Synopsys Tools Physical Design Fundamentals VLSI Basics
Applied ML Engineer — Circuit Design (New College Grad 2026) (NVIDIA)
✅ Fresher FriendlyAI Silicon
Machine Learning Circuit Design Python AI/ML Fundamentals
Senior Verification Engineer — ARM Fabric Unit (NVIDIA)
Verification
SystemVerilog UVM ARM Architecture Formal Verification Python
Digital Logic Design Apprenticeship
✅ Fresher FriendlyRTL Design
Digital Logic Design Verilog RTL ASIC Design EDA Tools
ASIC Physical Design Apprenticeship
✅ Fresher FriendlyPhysical Design
Physical Design Place & Route DRC LVS Timing P&R
Immediate Hiring for RTL Design Engineers
RTL Design
RTL Design Verilog SystemVerilog PCIe CXL Micro-architecture
Immediate Hiring for ASIC DV Engineers
Verification
SystemVerilog UVM ASIC Verification Coverage Assertions
CPU Design Engineer - New College Grad 2026
✅ Fresher FriendlyRTL Design
RTL Verilog SystemVerilog Micro-architecture ASIC Design
Senior ASIC Design Engineer — Agentic AI SoC
ASIC Design
ASIC Design RTL Verilog Agentic AI SoC GPU Architecture
ASIC Physical Design Engineer - New College Grad 2026
✅ Fresher FriendlyPhysical Design
Physical Design Place & Route STA Timing P&R Tools
Design Verification Engineer – PCIe/CXL Protocol
Verification
SystemVerilog UVM PCIe CXL Protocol SoC Verification
Pre-Si Verification Engineer — Compute Die Frontend
Verification
SystemVerilog Pre-Si Verification SoC Verification UVM Formal Verification
DFX Verification Engineer
DFT
DFX DFT Verification SystemVerilog Test Patterns
Design Verification Engineer (Mirafra Technologies)
✅ Fresher FriendlyVerification
SystemVerilog UVM Testbench Development VLSI Testing
Semiconductor Technical Hiring — RTL & DFT (Cyient)
DFT
RTL Design DFT Verilog Scan Design ATPG
ASIC Physical Design Apprenticeship (Synopsys)
✅ Fresher FriendlyPhysical Design
Physical Design P&R Timing Layout Verification
GPU Design Verification Sr Lead Engineer (Qualcomm)
Verification
SystemVerilog UVM GPU Verification SoC Testing Leadership
Senior ASIC Design Engineer — Agentic AI SoC (NVIDIA)
RTL Design
ASIC Design RTL Verilog Systemverilog Synthesis Timing Analysis
ASIC Design Engineer — GPU Memory Systems (NVIDIA)
RTL Design
RTL Design Verilog Logic Synthesis Timing ECO
Design Verification Engineer — New College Grad (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM Testbench Verification Python
Senior Verification Engineer — Hardware (NVIDIA, Bengaluru)
Verification
SystemVerilog UVM Hardware Verification GPU Testing
Associate Engineer — Modem Development (Qualcomm)
✅ Fresher FriendlyDesign Verification
C++ Python Signal Processing Embedded Systems
Lead Physical Design Engineer — AI NPU (NXP)
Physical Design
Physical Design P&R Synthesis STA Timing Closure
Associate Engineer — Modem Development (Qualcomm)
✅ Fresher FriendlySoC Architecture
Embedded Software Modem Architecture SoC Platform C/C++
Mixed Signal Design Verification Engineer (Intel)
Verification
Analog Circuit Design Mixed-Signal IP Floorplanning Advanced Process Nodes
Physical Design Engineer — ASIC Signoff (HCLTech)
Physical Design
Place & Route STA Physical Verification ICC2 PrimeTime
VLSI Engineer L3 — RTL & Digital Design (Wipro)
✅ Fresher FriendlyRTL Design
Verilog RTL Design Digital Logic VLSI Fundamentals
ASIC Design Engineer — High Speed IO (NVIDIA)
AI Silicon
Micro-architecture RTL Development High-Speed IO SerDes
FPGA Prototyping Engineer — Pre-Silicon Bring-up (Modernize Chip Solutions)
FPGA
FPGA Prototyping HAPS Emulation Hardware Debugging High-Speed Interfaces
Senior Quantum Engineer — Photonic Integrated Circuits (amPICQ)
Photonics
Photonic Integrated Circuits PIC Characterization Quantum Devices Optical Systems
CAD DV Senior Engineer, Lead — EDA Infrastructure (Qualcomm)
EDA Tools
EDA Tools CAD Flows Digital/Analog Verification Yield Bring-up
Jr. Package Design Engineer — Advanced IC Packaging (ASIP Technologies)
✅ Fresher FriendlyPackaging
Package Design VLSI Packaging Basics Substrate Design
DFT Engineer — Scan, MBIST & TAP (Intel)
DFT
DFT Scan MBIST TAP ATPG Client Engineering
Senior Physical Design Engineer — Google Cloud (Google)
Physical Design
Physical Design STA Place & Route Floorplanning TCL SystemVerilog
CAD AI Infrastructure Engineer — SoC/IP VLSI (Synopsys)
EDA Tools
CAD Infrastructure EDA Tools Python TCL AI/ML HPC VLSI Flows
Analog Design Engineer — Mixed-Signal SoC, Wireless Infrastructure (Texas Instruments)
Analog/Mixed-Signal
Analog Design Mixed-Signal OTA Comparators CMOS SPICE Cadence Virtuoso
Lead Product Validation Engineer — EDA & VLSI (Cadence)
Verification
Verilog SystemVerilog UVM C/C++ EDA Validation Product Testing
Pre-Si SoC Verification Engineer — Compute Die Frontend (Intel)
Verification
SystemVerilog UVM SoC Verification Pre-Silicon Validation Python
ASIC Physical Design & Timing Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Physical Design Timing Analysis STA Floorplanning Place & Route TCL
Design Engineer — HBM DFT, New College Grad (Micron Technology)
✅ Fresher FriendlyDFT
DFT ATPG Scan Insertion MBIST HBM Verilog
Senior Engineer — GPU RTL Design (Samsung Semiconductor)
RTL Design
RTL Design Verilog SystemVerilog GPU Architecture Synthesis Low Power Design
Staff RTL Design Engineer — NOC/Interconnect (Qualcomm)
SoC Architecture
RTL Design NOC AXI CHI ACE Interconnect SystemVerilog SoC Architecture
ASIC Design Engineer Graduate — Video Silicon IP, 2026 Start (ByteDance)
✅ Fresher FriendlyAI Silicon
ASIC Design RTL Verilog Video Codec Silicon IP Synthesis
Digital Logic Design Apprenticeship — ASIC & RTL (Synopsys)
✅ Fresher FriendlyRTL Design
Digital Logic Design Verilog SystemVerilog RTL Fundamentals ASIC Flows
Associate Engineer — Systems Design Engineering, NAND Storage (SanDisk)
✅ Fresher FriendlySoC Architecture
Systems Engineering NAND Storage Digital Design Python Hardware Validation
GPU Core Pipeline IP Verification Engineer (NVIDIA)
Verification
SystemVerilog UVM Python ASIC Verification Graphics IP
Software Engineer, Hardware Tools & Methodology — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyEDA Tools
Python Tcl RTL Design EDA Tools VLSI Flows Software Engineering
Senior Verification Engineer — IP & SoC Platform (ARM)
Verification
SystemVerilog UVM IP Verification SoC Verification Formal Verification
GPU Physical Design Engineer — Snapdragon SoC (Qualcomm)
Physical Design
Physical Design Place & Route Floorplanning CTS STA Innovus ICC2
Lead Physical Design Engineer — CPU/GPU High-Performance IP (AMD)
Physical Design
Physical Design Place & Route CPU/GPU IP STA Power Analysis ECO
High-Speed RTL Design Engineer — Memory Interface SoC (Micron)
RTL Design
Verilog SystemVerilog RTL Design High-Speed I/O Memory Interfaces Synthesis
SoC Security Engineer — Platform Architecture (Apple)
SoC Architecture
Security Architecture SoC Design Hardware Security Cryptography SystemVerilog
Hardware Design Intern — FPGA Digital Design (Lattice Semiconductor)
✅ Fresher FriendlyFPGA
Verilog FPGA Design Digital Logic HDL Lattice Tools
Physical Verification Engineer — ASIC Signoff, Entry Level (SEMIFIVE)
✅ Fresher FriendlyPhysical Design
Physical Verification DRC LVS ERC Calibre IC Validator ASIC Signoff
VLSI CAD Engineer — HPC & EDA Infrastructure (NVIDIA)
EDA Tools
VLSI CAD EDA Tools HPC Linux Python Perl Scripting Design Flows
IP RTL Design Engineer — Memory-PHY & High-Speed Interface (Samsung)
RTL Design
RTL Design Verilog SystemVerilog Memory PHY ASIC Design Synthesis STA
IP Design Verification Engineer — Entry Level (Intel)
✅ Fresher FriendlyVerification
SystemVerilog UVM Design Verification Testbench Development Microarchitecture
GPU Design Verification Engineer — AI Graphics SoC (MediaTek)
AI Silicon
SystemVerilog UVM GPU Verification 3D Graphics Pipeline Compute Workloads Python
DFT Engineer — Snapdragon SoC Platform (Qualcomm)
DFT
DFT Scan Insertion ATPG JTAG Boundary Scan BIST Coverage Analysis
Mac Hardware Systems Engineer — SoC Platform (Apple)
SoC Architecture
SoC Design Hardware Systems CPU Architecture Memory Subsystems Power Analysis Python
FPGA Design Engineer — Networking SoC (Cisco)
FPGA
FPGA Xilinx Altera Verilog VHDL RTL Design Timing Analysis Network SoC
EDA Engineering Intern — FPGA Tools & Flows (Lattice Semiconductor)
✅ Fresher FriendlyEDA Tools
EDA Tools FPGA Verilog VHDL Scripting TCL Python ASIC Design Flow
DFT Engineer — GPU Silicon Verification (NVIDIA)
✅ Fresher FriendlyDFT
DFT ATPG Scan Insertion SystemVerilog UVM Python Formal Verification
Staff Design Verification Engineer — Snapdragon SoC (Qualcomm)
Verification
SystemVerilog UVM Formal Verification Snapdragon SoC Python Coverage-Driven Verification
Mixed Signal Logic Design Engineer — Advanced SoC (Intel)
RTL Design
Mixed Signal Design Verilog SPICE AMS Verification Logic Design RTL STA
Senior DFT Engineer — Automotive SoC (NXP Semiconductors)
DFT
DFT Architecture ATPG Scan Design BIST JTAG IEEE 1500 SoC DFT
Staff RTL Design Engineer — PCIe IP (Marvell Technology)
RTL Design
RTL Design SystemVerilog PCIe Gen5/Gen6 SoC Integration Micro-architecture CDC/RDC
Senior FPGA Design Engineer — Satellite Signal Processing (Dhruva Space)
FPGA
FPGA Xilinx/Intel FPGA VHDL Verilog DSP SpaceWire High-Speed Serial Links
Associate Engineer I — CAD & EDA Tools, Fresher (Silicon Labs)
✅ Fresher FriendlyEDA Tools
EDA Tools CAD Scripting Python Perl Tcl Digital Design ASIC Flow Automation
Physical Design Engineer — Entry Level, ASIC SoC (Renesas Electronics)
✅ Fresher FriendlyPhysical Design
Physical Design Floorplanning Placement & Routing STA Cadence Innovus Synopsys ICC2
Associate II — VLSI Design & Verification, Fresher (UST)
✅ Fresher FriendlyVerification
Verilog SystemVerilog UVM Digital Design ASIC Verification Python Scripting
Senior ASIC Design Engineer — Agentic AI SoC (NVIDIA)
AI Silicon
RTL Design SystemVerilog ASIC Architecture AI SoC Micro-architecture DV
Silicon AI/ML DFT Engineer, Google Cloud (Google)
DFT
DFT ATPG Scan Compression AI/ML Hardware TPU JTAG Boundary Scan
Lead Physical Design Engineer — AI NPU SoC Implementation, India (NXP Semiconductors)
Physical Design
Physical Design Floorplan Place & Route STA Power Analysis Clock Tree Synthesis AI NPU
Physical Design Engineer — RTL to GDS & FPGA Integration, Hyderabad (Altera)
FPGA
Physical Design Place & Route STA DFT RTL GDS FPGA Architecture
Lead Hardware Engineer — DFT IP R&D & MODUS Software, India (Cadence)
EDA Tools
DFT ATPG Scan Compression MODUS DFT SystemVerilog TCL EDA Tools
Senior Package Layout Engineer — Advanced ASIC & HBM Packaging, Bengaluru (NVIDIA)
Packaging
IC Packaging Substrate Layout Signal Integrity HBM Cadence Allegro ASIC Package Design
Staff Engineer — ASIC Validation & FPGA Emulation, India (Micron Technology)
Verification
FPGA Xilinx Ultrascale HAPS Protocompiler SoC Validation Vivado Pre-Silicon Validation
FPGA Validation Engineer — Functional & Electrical Testing, Hyderabad (ACL Digital)
✅ Fresher FriendlyFPGA
FPGA Validation Test Plans Functional Testing Electrical Testing Hardware Debugging
Field Application Engineer — EDA Tools & VLSI Design Flow, India (Siemens EDA)
✅ Fresher FriendlyEDA Tools
EDA Tools VLSI Design Questa Simulation Calibre Tcl Scripting Customer Support
DFT Design Engineer — Entry Level, Scan & ATPG, Bengaluru (ChipNova Semiconductors)
✅ Fresher FriendlyDFT
DFT ATPG Scan Insertion JTAG Boundary Scan Verilog SystemVerilog
Formal & Design Verification Engineers — UVM & C++ Testbench, Hyderabad (AMD)
Verification
SystemVerilog UVM C++ Formal Verification JasperGold Simulation
SoC Verification Engineer — Full Chip SoC Validation, Bengaluru (Tesla)
Verification
SystemVerilog UVM SoC Verification Python SV Assertions Functional Coverage
RFIC Design Engineer — Wireless Transceiver SoC 4G/5G (Texas Instruments)
AI Silicon
RFIC Design Analog Circuit Design RF Transceiver Cadence Virtuoso Spectre Simulation
Principal RTL Design Engineer — Embedded SoC, Noida (STMicroelectronics)
RTL Design
RTL Design VHDL SystemVerilog Synthesis Timing Closure ARM Cortex FPGA Prototyping
PCIe Design Engineer — VLSI SoC Architecture, Bengaluru (Broadcom)
SoC Architecture
PCIe VLSI Design SoC Architecture Digital Design Verilog SystemVerilog Python
VLSI Physical Design Intern — IC Design Tools & Flows (Cadence)
✅ Fresher FriendlyPhysical Design
Physical Design Floorplanning CTS Routing Cadence Innovus STA
Silicon Design Engineer 1 — DV & RTL Verification, Delhi (AMD)
✅ Fresher FriendlyVerification
SystemVerilog UVM RTL Verification SoC Debug Python
Design Verification Engineer — Silicon & Systems Group, Bengaluru (Amazon Lab126)
Verification
SystemVerilog UVM Python ASIC Verification SoC Debug Formal Verification
DFT Engineer — ATPG & Scan, Bengaluru (AMD)
DFT
DFT ATPG Scan Insertion BIST Mentor Tessent Synopsys DFT Compiler Python
ASIC Design Engineer — RTL & Micro-architecture, Bengaluru (NVIDIA)
RTL Design
RTL Design SystemVerilog Python Micro-architecture Synthesis ASIC Design
DFT Design Engineer — Scan & JTAG, Bengaluru (Intel)
DFT
DFT ATPG Scan Chain JTAG Boundary Scan Tessent TestKompress Verilog
Design Verification Engineer — VLSI Fresher & Experienced (Innovidia Technologies)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verilog Digital Electronics Functional Verification
Senior IP Verification Engineer — Memory & Ethernet VIP Development (Siemens EDA)
EDA Tools
UVM VIP Development SystemVerilog Ethernet DDR/LPDDR Verification IP Protocol Verification
Senior Technical Staff Engineer — SoC Architecture & ARM Cortex Design, Bengaluru (Microchip Technology)
SoC Architecture
SoC Architecture ARM Cortex AMBA Microcontroller Design RTL Synthesis Timing Closure
Design Verification Engineer — Entry Level, ASIC & SoC Platform (PurnaSemi)
✅ Fresher FriendlyVerification
SystemVerilog UVM SoC Verification Verilog Python Assertion-Based Verification
Applications Engineering Engineer — EDA & VLSI Design Tools (Synopsys)
✅ Fresher FriendlyEDA Tools
EDA Tools Synthesis RTL Simulation Tcl Scripting Python Digital Design Flow
Software Engineer — AI Models & HDL Design Workflows, Hyderabad (AMD)
AI Silicon
HDL Python C++ EDA Tools AI/ML Models Digital Design Verilog
Senior GPU Floorplan Design Engineer — Physical Design, Bengaluru (NVIDIA)
Physical Design
Physical Design Floorplanning Place & Route STA Power Analysis IC Compiler II Innovus
Senior Pre-Silicon DFT & Design Verification Engineer — AI SoC Platform (ARM)
DFT
DFT ATPG Scan Insertion Siemens Tessent SystemVerilog Gate-Level Simulation Boundary Scan
Staff RTL Design Engineer — SMMU & SoC Memory Subsystem, Bengaluru (Qualcomm)
RTL Design
RTL Design SystemVerilog SMMU AMBA AXI/AHB SoC Integration Memory Management Unit
FPGA Design Verification Engineer — Networking & SoC Platform, Bengaluru (Cisco)
FPGA
FPGA Verilog SystemVerilog OOP Verification UVM Networking Protocols Xilinx/Vivado
VLSI Design Engineer — Entry Level, RTL & Digital IP (PrimeSoc Technologies)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design Digital Design ASIC Flow Synopsys DC
Senior IP Verification Engineer — Memory & Ethernet VIP Development (Siemens EDA)
EDA Tools
UVM VIP Development SystemVerilog Ethernet DDR/LPDDR Verification IP Protocol Verification
Senior Technical Staff Engineer — SoC Architecture & ARM Cortex Design, Bengaluru (Microchip Technology)
SoC Architecture
SoC Architecture ARM Cortex AMBA Microcontroller Design RTL Synthesis Timing Closure
Design Verification Engineer — Entry Level, ASIC & SoC Platform (PurnaSemi)
✅ Fresher FriendlyVerification
SystemVerilog UVM SoC Verification Verilog Python Assertion-Based Verification
Applications Engineering Engineer — EDA & VLSI Design Tools (Synopsys)
✅ Fresher FriendlyEDA Tools
EDA Tools Synthesis RTL Simulation Tcl Scripting Python Digital Design Flow
Software Engineer — AI Models & HDL Design Workflows, Hyderabad (AMD)
AI Silicon
HDL Python C++ EDA Tools AI/ML Models Digital Design Verilog
Senior GPU Floorplan Design Engineer — Physical Design, Bengaluru (NVIDIA)
Physical Design
Physical Design Floorplanning Place & Route STA Power Analysis IC Compiler II Innovus
Senior Pre-Silicon DFT & Design Verification Engineer — AI SoC Platform (ARM)
DFT
DFT ATPG Scan Insertion Siemens Tessent SystemVerilog Gate-Level Simulation Boundary Scan
Staff RTL Design Engineer — SMMU & SoC Memory Subsystem, Bengaluru (Qualcomm)
RTL Design
RTL Design SystemVerilog SMMU AMBA AXI/AHB SoC Integration Memory Management Unit
FPGA Design Verification Engineer — Networking & SoC Platform, Bengaluru (Cisco)
FPGA
FPGA Verilog SystemVerilog OOP Verification UVM Networking Protocols Xilinx/Vivado
VLSI Design Engineer — Entry Level, RTL & Digital IP (PrimeSoc Technologies)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design Digital Design ASIC Flow Synopsys DC
EDA Methodology & Application Engineer — Design Compiler, India (IBM)
EDA Tools
Synopsys DC/DCNXT Logic Synthesis Timing Closure TCL VLSI Design Flow Python
Senior Physical Design Engineer — Digital ASIC for 5G Network, India (Ericsson)
Physical Design
Place-and-Route CTS STA Floorplanning DRC LVS Physical Design Signoff Cadence Innovus
ASIC Engineer — Silicon Photonics Driver ASIC, Bengaluru (Cisco)
Photonics
ASIC Design Silicon Photonics Physical Design Mixed-Signal CMOS Optical Integration Cadence
ASIC Verification Engineer — Entry Level, AI Chip & GPU (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM Functional Verification Python Simulation Hardware Debugging
Physical Design Engineer — Entry Level VLSI & SoC, India (Texas Instruments)
✅ Fresher FriendlyPhysical Design
Physical Design Logic Synthesis Floorplanning CTS STA Cadence Tools Verilog
Silicon Engineer — Platform & Devices, University Graduate 2026 (Google)
✅ Fresher FriendlyAI Silicon
SoC Design RTL Design Verilog SystemVerilog Computer Architecture VLSI Python
R&D Sr Staff Engineer — RTL Design & Verification, Bengaluru (Synopsys)
RTL Design
RTL Design SystemVerilog UVM Verilog Formal Verification Python Simulation
Infra Design Verification Sr Lead Engineer — Snapdragon SoC, Bengaluru (Qualcomm)
Verification
SystemVerilog UVM Verification Infrastructure Python TCL Coverage-Driven Verification
Senior DFT Verification Engineer — GPU & AI SoC (NVIDIA)
DFT
DFT ATPG Scan Insertion JTAG Boundary Scan SystemVerilog Static Timing Analysis
FPGA Prototyping & Emulation Developer — SoC Pre-Silicon, Bengaluru (Micron Technology)
FPGA
FPGA SoC Prototyping Emulation Verilog SystemVerilog Python Hardware Debugging
Staff DFT Engineer — VLSI Design Flow & Sign-off, Bhubaneswar (Synopsys)
DFT
DFT ATPG Scan Insertion Boundary Scan JTAG Tessent Synopsys DFT Compiler
Principal Hardware DFT Lead — Automotive SoC, Noida (NXP Semiconductors)
DFT
DFT Architecture ATPG MBIST Scan Compression BSCAN Tessent Synopsys DFT
Senior Staff Engineer — AMS IP Verification, India (Marvell Technology)
Verification
AMS Verification Mixed-Signal Design SystemVerilog Spectre Verilog-AMS UVM
RTL Design Graduate Intern — AI Inference Chip, Bengaluru (Tesla)
✅ Fresher FriendlyAI Silicon
Verilog SystemVerilog RTL Design Digital Logic Python ML Accelerator Architecture
RTL Design Engineer — ASIC & Digital IP, Bengaluru (BitSilica)
✅ Fresher FriendlyRTL Design
RTL Design Verilog SystemVerilog Digital Logic VLSI FPGA Synthesis
Power Architecture Engineer — GPU & AI SoC Platform, Bengaluru (NVIDIA)
AI Silicon
Low Power Design Power Analysis RTL Design ASIC Architecture Python Perl
IP Verification Engineer — Digital Hardware Design, Bengaluru (Intel)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verilog Python Scripting Functional Verification
Physical Design Engineer — Advanced SoC Implementation, Bengaluru (Intel)
Physical Design
Place & Route STA Floorplanning CTS Routing Virtuoso Innovus
SoC Physical Design Verification Engineer — Apple Silicon, Austin (Apple)
Physical Design
Physical Verification DRC LVS ERC Calibre IC Validator VLSI Back-end Flow
Graphics IP RAS Engineer — GPU Silicon Design (AMD)
AI Silicon
RTL Design Verilog Computer Architecture VLSI Digital Logic C/C++
Staff DFT Engineer — VLSI Design Flow & Sign-off, Bhubaneswar (Synopsys)
DFT
DFT ATPG Scan Insertion Boundary Scan JTAG Tessent Synopsys DFT Compiler
Principal Hardware DFT Lead — Automotive SoC, Noida (NXP Semiconductors)
DFT
DFT Architecture ATPG MBIST Scan Compression BSCAN Tessent Synopsys DFT
Senior Staff Engineer — AMS IP Verification, India (Marvell Technology)
Verification
AMS Verification Mixed-Signal Design SystemVerilog Spectre Verilog-AMS UVM
RTL Design Graduate Intern — AI Inference Chip, Bengaluru (Tesla)
✅ Fresher FriendlyAI Silicon
Verilog SystemVerilog RTL Design Digital Logic Python ML Accelerator Architecture
RTL Design Engineer — ASIC & Digital IP, Bengaluru (BitSilica)
✅ Fresher FriendlyRTL Design
RTL Design Verilog SystemVerilog Digital Logic VLSI FPGA Synthesis
Power Architecture Engineer — GPU & AI SoC Platform, Bengaluru (NVIDIA)
AI Silicon
Low Power Design Power Analysis RTL Design ASIC Architecture Python Perl
IP Verification Engineer — Digital Hardware Design, Bengaluru (Intel)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verilog Python Scripting Functional Verification
Physical Design Engineer — Advanced SoC Implementation, Bengaluru (Intel)
Physical Design
Place & Route STA Floorplanning CTS Routing Virtuoso Innovus
SoC Physical Design Verification Engineer — Apple Silicon, Austin (Apple)
Physical Design
Physical Verification DRC LVS ERC Calibre IC Validator VLSI Back-end Flow
Graphics IP RAS Engineer — GPU Silicon Design (AMD)
AI Silicon
RTL Design Verilog Computer Architecture VLSI Digital Logic C/C++
STA Engineer — Snapdragon SoC Platform, Bengaluru (Qualcomm)
Physical Design
STA PrimeTime Low Power Timing Closure VLSI Physical Design SDC
Principal DFT Engineer — Mixed-Signal SoC, Bengaluru (Analog Devices)
DFT
DFT Scan Chains BIST ATPG JTAG Mixed-Signal Testing Tessent
Principal Engineer — VLSI Design Verification, NAND Memory (SanDisk)
Verification
SystemVerilog UVM NAND Flash Verification RTL Simulation Verilog Formal Verification
Low Power ASIC Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyAI Silicon
RTL Design Low Power Techniques Power Analysis Verilog Python
Verification and Validation Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM C++ Computer Architecture Python
Deep Learning Computer Architect — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlySoC Architecture
Deep Learning Computer Architecture GPU Architecture RTL Python CUDA
Senior Silicon Engineer — gCPU Design Verification, Multiple Openings (Google)
Verification
SystemVerilog UVM CPU Verification SoC Design Python C++
Senior Silicon CAD Tool Developer (Google)
EDA Tools
Python TCL EDA Flow Development VLSI Design Flow CAD Scripting
Senior RTL Design Lead — CPU Team, Bangalore (AMD)
RTL Design
RTL Design Verilog SystemVerilog STA CPU Microarchitecture VLSI
SoC Verification Manager/Lead — Bangalore (AMD)
Verification
SoC Verification SystemVerilog UVM Test Planning Verification Management Coverage
Design Engineer II — Physical Design & SoC IP Implementation (Cadence)
Physical Design
Cadence Genus Innovus Tempus Voltus Place & Route CTS STA Floorplanning
SOC RTL Design Engineer — System LSI & Memory Platform (Samsung India)
RTL Design
SystemVerilog Verilog RTL Design Low Power UPF ASIC SoC Synthesis
SRAM Design Engineer — xPU Cache Architecture (MediaTek)
AI Silicon
SRAM Design FCI Design CPU/GPU Memory Systems DRC/LVS SPICE Memory Characterization
Analog EDA Lead Engineer — CAD & IC Design Tools (Texas Instruments)
Analog Design
Cadence Virtuoso Analog EDA Mixed-Signal Design SPICE Simulation CAD Scripting Python
VLSI Engineer L3 — Digital Design & RTL Implementation (Wipro)
RTL Design
SystemVerilog Verilog RTL Design ASIC Flow Synthesis Timing Analysis
Senior CAD Engineer — Digital Verification Infrastructure & EDA (NXP Semiconductors)
Verification
EDA Tools Verification Infrastructure SystemVerilog Python CAD Automation SoC IP
ASIC Clocks Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlySoC Architecture
Verilog SystemVerilog Clock Tree Synthesis STA Low Power Design Python
HW Design Intern — FPGA & Digital ASIC (Lattice Semiconductor)
✅ Fresher FriendlyFPGA
Verilog FPGA Design Digital Logic SystemVerilog EDA Tools
Software Engineer — Hardware Tools & Methodology, New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyEDA Tools
Python Verilog ASIC Design Flow EDA Tools CAD Automation RTL
CPU Design Senior Staff Verification Engineer — Snapdragon SoC (Qualcomm)
Verification
SystemVerilog UVM CPU Verification SoC Verification Formal Verification Python
VLSI Engineers — Circuit Design & DFT Implementation, Bengaluru (LanceSoft)
DFT
VLSI Design DFT Scan Insertion Circuit Design Logic Implementation Synopsys Tools
ASIC Design Engineer — ML Processor & Digital IP (AMD)
AI Silicon
RTL Design SystemVerilog Machine Learning Accelerators STA Physical Design Interface
Physical Design & Implementation Engineer — Automotive SerDes SoCs (Texas Instruments)
Physical Design
Physical Design Floorplanning Place & Route STA High-Speed SerDes Low-Power VLSI
Design Verification Engineer — Advanced SoC Platform (ElevarSoC Technologies)
Verification
SystemVerilog UVM Assertion-Based Verification Functional Coverage Simulation Tools
Principal CAD AI Infrastructure Engineer — SoC/IP VLSI Platform (Synopsys)
EDA Tools
EDA Tools Python Tcl VLSI CAD Infrastructure SoC IP Enablement AI-Driven Design Automation
ASIC Design Engineer Graduate — Video Silicon IP 2026 (ByteDance)
✅ Fresher FriendlyAI Silicon
RTL Design Verilog SystemVerilog Video Codec Architecture ASIC Design Flow
VLSI Engineer I — Digital Design & SoC Implementation (Hewlett Packard Enterprise)
✅ Fresher FriendlyRTL Design
Verilog VLSI Design Fundamentals Digital Logic Computer Architecture RTL Coding
Senior Systems Prototyping & FPGA Emulation Engineer (NVIDIA)
FPGA
FPGA Prototyping Hardware Emulation RTL Partitioning Synopsys Zebu Palladium SoC Bring-up
Engineer — Hardware Engineering, SoC Design (ARM)
✅ Fresher FriendlySoC Architecture
SoC Architecture Digital Design RTL Verilog/SystemVerilog ARM IP Integration
Verification Engineer — GPU Fullchip SoC Platform, Bengaluru (NVIDIA)
Verification
SystemVerilog UVM SoC Verification Python Coverage-Driven Verification
Staff Engineer — ASIC Silicon Validation & Memory Interface (Micron Technology)
Verification
ASIC Validation HAPS Prototyping FPGA Silicon Debug Memory Protocols (HBM/DDR)
IP RTL Design Engineer — High-Speed Compute SoC (Marvell Technology)
RTL Design
RTL Design Verilog SystemVerilog Microarchitecture CDC Verification
Senior Physical Design Engineer — Advanced VLSI Chip Implementation (HCL Tech)
Physical Design
Physical Design Place & Route STA Cadence Innovus Power Analysis
Design Verification Engineer — NoC & Interconnect SoC Platform (BitSilica)
Verification
SystemVerilog UVM NoC Verification Functional Coverage Assertion-Based Verification
VLSI CAD Engineer — SoC IP Enablement & Front-End TFM (L&T Semiconductor)
EDA Tools
EDA Tools Synopsys Design Compiler Cadence Genus TCL Scripting IP Integration
ASIC Physical Design Apprenticeship — Fresher 2024/2025 Batch (Synopsys)
✅ Fresher FriendlyPhysical Design
Physical Design Fundamentals Synopsys Fusion Compiler STA Basics Verilog Linux
ASIC Design Engineer — Entry Level FPGA & Logic Design (Lattice Semiconductor)
✅ Fresher FriendlyFPGA
Verilog FPGA Design RTL Synthesis Timing Analysis ASIC Flows
VLSI Engineer L2 — RTL & Digital Design Implementation (Wipro)
✅ Fresher FriendlyRTL Design
VLSI Design SystemVerilog RTL Simulation Verilog Digital Logic
Senior Staff RTL Design Engineer — Snapdragon Peripheral SoC (Qualcomm)
RTL Design
RTL Design SystemVerilog Peripheral IP Microarchitecture Low-Power Design
Senior SoC Design Engineer — AI Networking Group, Bangalore (NVIDIA)
SoC Architecture
RTL Design SystemVerilog SoC Architecture Networking IP PPA Optimization
RTL Design Engineer — Entry Level, ASIC & FPGA Design (IndieSemiC)
✅ Fresher FriendlyRTL Design
RTL Design Verilog SystemVerilog FPGA ASIC Synthesis Simulation
Mixed Signal Design Verification Engineer — Advanced SoC (Intel)
Verification
Mixed Signal Verification SystemVerilog UVM Analog-Digital Co-Simulation SPICE
Senior DFT Engineer — GPU & Server SoC Platform, Bangalore (AMD)
DFT
DFT ATPG JTAG Boundary Scan Scan Insertion MBIST Tessent
Senior RTL Design Engineer — CPU & GPU SoC Integration, Hyderabad (AMD)
RTL Design
RTL Design Verilog SystemVerilog Logic Synthesis STA ARM Architecture
DFT Engineer — High-Speed Automotive SerDes SoC (Texas Instruments)
DFT
DFT ATPG SerDes Automotive ASIC MBIST Boundary Scan JTAG
DFT Engineer — Custom Silicon ASIC Design-to-Production (Tesla)
DFT
DFT RTL Implementation Scan Integration JTAG Custom ASIC Python
High-Speed RTL Design Engineer — Memory Interface SoC, Entry Level (Micron)
✅ Fresher FriendlyRTL Design
RTL Design Verilog SystemVerilog DDR LPDDR High-Speed Memory Interface
Lead Physical Design Engineer — AI NPU SoC Implementation (NXP Semiconductors)
Physical Design
Physical Design Floorplanning Place & Route CTS STA AI NPU Innovus
ASIC Verification Engineer — GPU & AI SoC Platform, Hyderabad (NVIDIA)
Verification
SystemVerilog UVM Python Gate-Level Simulation Assertion-Based Verification
ASIC Design Engineer — Entry Level, AI & Compute SoC India (NVIDIA)
✅ Fresher FriendlyAI Silicon
RTL Design SystemVerilog ASIC Verification Python Logic Synthesis
Lead Physical Design Engineer — AI NPU SoC Implementation (NXP Semiconductors)
Physical Design
Physical Design Floorplanning Place & Route CTS STA AI NPU Innovus
RTL Design Engineer — Entry Level, ASIC & FPGA Design (IndieSemiC)
✅ Fresher FriendlyRTL Design
RTL Design Verilog SystemVerilog FPGA ASIC Synthesis Simulation
ASIC Verification Engineer — GPU & AI SoC Platform, Hyderabad (NVIDIA)
Verification
SystemVerilog UVM Python Gate-Level Simulation Assertion-Based Verification
ASIC Design Engineer — Entry Level, AI & Compute SoC India (NVIDIA)
✅ Fresher FriendlyAI Silicon
RTL Design SystemVerilog ASIC Verification Python Logic Synthesis
Mixed Signal Design Verification Engineer — Advanced SoC (Intel)
Verification
Mixed Signal Verification SystemVerilog UVM Analog-Digital Co-Simulation SPICE
Senior DFT Engineer — GPU & Server SoC Platform, Bangalore (AMD)
DFT
DFT ATPG JTAG Boundary Scan Scan Insertion MBIST Tessent
Senior RTL Design Engineer — CPU & GPU SoC Integration, Hyderabad (AMD)
RTL Design
RTL Design Verilog SystemVerilog Logic Synthesis STA ARM Architecture
DFT Engineer — High-Speed Automotive SerDes SoC (Texas Instruments)
DFT
DFT ATPG SerDes Automotive ASIC MBIST Boundary Scan JTAG
DFT Engineer — Custom Silicon ASIC Design-to-Production (Tesla)
DFT
DFT RTL Implementation Scan Integration JTAG Custom ASIC Python
High-Speed RTL Design Engineer — Memory Interface SoC, Entry Level (Micron)
✅ Fresher FriendlyRTL Design
RTL Design Verilog SystemVerilog DDR LPDDR High-Speed Memory Interface
Associate Engineer — IC Design, Mixed-Signal SoC (Silicon Labs)
✅ Fresher FriendlySoC Architecture
Verilog ASIC Design Digital Logic IC Design Fundamentals Python SPICE Simulation
Associate II — VLSI Design & Verification (UST)
✅ Fresher FriendlyVerification
SystemVerilog Verilog RTL Design Functional Verification ASIC Design UVM basics
Associate III — VLSI Engineer, RTL & Physical Design (UST)
✅ Fresher FriendlyPhysical Design
VLSI Design Verilog Physical Design Basics RTL Coding EDA Tools Synthesis
GPU Core Pipeline IP Verification Engineer — ASIC Chip Verification (NVIDIA)
Verification
SystemVerilog UVM GPU Verification Python Constrained Random Coverage-Driven Verification
Senior ASIC Power Engineer — GPU SoC RTL Design & Power Optimization (NVIDIA)
RTL Design
SystemVerilog RTL Design Power Analysis Low-Power Techniques ASIC Synthesis STA
Semicustom DFT Strategy Lead — Design for Test & Debug Methodology (AMD)
DFT
DFT ATPG Scan Chain JTAG Design for Debug LBIST Tessent Synopsys DFT Compiler
Wireless SOC Verification Engineer — 5G RF Silicon Verification (Apple)
Verification
SystemVerilog UVM Wireless SoC RF Verification Python 5G Protocol Constrained Random
Senior Physical Design Engineer — Digital ASIC SoC Implementation (NXP Semiconductors)
Physical Design
Physical Design Floorplanning Place & Route CTS STA Synopsys ICC2 Innovus DRC/LVS
DFT Engineer — Snapdragon SoC Platform, Hyderabad (Qualcomm)
DFT
DFT ATPG Scan Insertion MBIST Boundary Scan Tessent Synopsys DFT RTL Design
ASIC RTL Engineer III — Silicon AI Accelerator Platform (Google)
AI Silicon
RTL Design SystemVerilog ASIC Design DFT Synthesis Timing Analysis Python AI Hardware
CAD/EDA Tools Automation Engineer — New Grad 2026 (Intel)
✅ Fresher FriendlyEDA Tools
Python TCL EDA Automation CAD Tools Perl Git Linux VLSI Design Flow Scripting
Senior Design Engineer — Verification, New College Grad 2026 (GlobalFoundries)
✅ Fresher FriendlyVerification
SystemVerilog UVM SPICE Simulation Mixed-Signal Verification Python Perl
FPGA Machine Learning Engineering Graduate Intern (Altera)
✅ Fresher FriendlyFPGA
FPGA RTL Design Verilog Machine Learning HLS Python Quartus Prime
Interconnect Micro-architect — RTL Design Engineer, GPU SoC (AMD)
RTL Design
RTL Design SystemVerilog Micro-architecture SoC Interconnect Network-on-Chip Python TCL
Field Application Engineer — Tessent Design for Test, DFT (Siemens EDA)
DFT
DFT Tessent ATPG MBIST Boundary Scan JTAG SystemVerilog TCL Python
Principal Application Engineer — RTL2GDS Physical Implementation (Cadence)
EDA Tools
Innovus Genus RTL2GDS Physical Design Timing Closure Python TCL Advanced Node ASIC
Principal Engineer — ASIC Design Verification, Silicon Photonics (Ayar Labs)
Photonics
SystemVerilog UVM Formal Verification Silicon Photonics Optical I/O Python Coverage-Driven Verification
Design Verification Engineer — APS Analog Mixed-Signal SoC (Texas Instruments)
Verification
Analog Mixed-Signal Verification SPICE SystemVerilog UVM Python Verilog-AMS Calibre
Software Engineer — SoC Level Validation, Apple Silicon (Apple)
SoC Architecture
SoC Validation Python C/C++ JTAG Hardware Debugging Post-Silicon Validation ARM Architecture
ASIC Physical Design Engineer — Netlisting, New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Physical Design Netlisting Static Timing Analysis Synopsys DC Cadence Innovus Python TCL
Analog IC Design Engineer — High-Speed SerDes & PHY (Marvell)
SoC Architecture
Analog IC Design CMOS Cadence Virtuoso SPICE SerDes PLL High-Speed IO
Design Verification Engineer — FPGA & ASIC SoC Platform (Altera)
FPGA
SystemVerilog UVM Verification FPGA Formal Verification Python
Senior LPU ASIC Engineer — AI Accelerator Chip Design (NVIDIA)
AI Silicon
ASIC Design RTL SystemVerilog Low Power Design AI Accelerators SoC Integration
RTL Design Graduate Intern — Digital SoC Design (Tesla)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design Digital Logic FPGA Prototyping
Circuit Design Engineer — Standard Cell Characterization, NCG 2026 (NVIDIA)
✅ Fresher FriendlyAI Silicon
Circuit Design SPICE Standard Cell Characterization CMOS Python
SoC Design Verification Engineer — Entry Level ASIC (Chiplogic Technologies)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verification SoC Digital Design
Senior DFT Engineer — GPU & SoC Test Architecture (AMD)
DFT
DFT ATPG Scan Insertion MBIST JTAG Tessent Synopsys DFT Compiler
Senior Physical Design Engineer — Advanced SoC Implementation (Samsung Semiconductor)
Physical Design
Physical Design Place & Route STA Timing Closure ICC2 Innovus Floorplanning
Embedded Memory Circuit Design Engineer — SRAM & IP Design (Synopsys)
EDA Tools
SRAM Design Circuit Design SPICE Memory Compilers CMOS Layout
Senior Engineer — Digital Design Engineering (Analog Devices)
RTL Design
Verilog SystemVerilog RTL Design FPGA Synthesis Digital Signal Processing
Engineer — DFT, Snapdragon SoC Platform (Qualcomm)
DFT
ATPG DFT JTAG SCAN Insertion MBIST IJTAG Tessent
Infra Design Verification Engineer — SoC Platform (Qualcomm)
Verification
SystemVerilog UVM Python Verification Infrastructure Coverage
Design Verification Engineer — Mixed-Signal Automotive SerDes SoC (Texas Instruments)
Verification
Mixed-Signal Verification SystemVerilog UVM SerDes SPICE Analog
SoC Physical Design Methodology Engineer — Apple Silicon (Apple)
Physical Design
Physical Design DRC/LVS Full-chip Integration EDA Scripting P&R
Design Verification Engineer — ASIC SoC Platform (EdgeSilica)
Verification
SystemVerilog UVM Constrained Random Functional Coverage Python
Associate Engineer I — HW Validation & Test (Silicon Labs)
✅ Fresher FriendlyVerification
Hardware Validation FPGA Lab Debugging Electronics Python Scripting
FPGA Design Engineer — Defense & Aerospace Applications (Aspire Spectrum)
✅ Fresher FriendlyFPGA
FPGA Design Verilog VHDL Xilinx Vivado Intel Quartus Embedded Systems
ASIC Verification Engineer — AI SoC Platform (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM ASIC Verification Python RTL Simulation
SoC RTL Design Engineer — Processor & IP Design (Intel)
RTL Design
RTL Design Verilog SystemVerilog SoC Integration Lint CDC
Senior Physical Design Engineer — Advanced ASIC SoC (Intel)
Physical Design
Place & Route STA Floor Planning Cadence Innovus Timing Closure
SoC Physical Design Engineer, STA/Timing — Apple Silicon (Apple)
Physical Design
STA Timing Closure Physical Design Synopsys PrimeTime Place & Route SDC Constraints
Principal Engineer — UI Architect, EDA/FPGA Tools (Lattice Semiconductor)
EDA Tools
EDA Tools FPGA UI Architecture C++ Python Qt Framework Tool Development
RFIC Design Engineer — Wireless Transceiver SoC 4G/5G (Texas Instruments)
AI Silicon
RFIC Design PLL LNA Mixer VGA RF Front-End Cadence Virtuoso
FPGA SW Validation Engineer — Altera FPGA Platform (Altera)
FPGA
FPGA Software Validation Python Tcl Quartus Hardware Validation Test Automation
VLSI Engineer I — RTL & Digital Design Implementation (Hewlett Packard Enterprise)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design ASIC Digital Logic Simulation
Senior DFT Verification Engineer — SoC Test Architecture (NVIDIA)
DFT
DFT JTAG BIST ATPG SystemVerilog RTL Simulation Gate-Level Netlist
DFT Verification Engineer — GPU Compute SoC (AMD)
DFT
DFT ATPG MBIST Scan Chain SystemVerilog Verilog
Silicon Design Verification Engineer — Google Cloud AI SoC (Google)
✅ Fresher FriendlyVerification
SystemVerilog UVM Python RISC-V Formal Verification Coverage-Driven Verification
Interim Engineering Intern — Systems & SoC Architecture 2026 (Qualcomm)
✅ Fresher FriendlySoC Architecture
SoC Architecture Verilog SystemVerilog C/C++ Python Digital Design
Wireless Systems Engineer — PHY & RF SoC (Qualcomm)
AI Silicon
PHY Layer RF Design Signal Processing 5G/4G Modem Wireless Architecture
IP Development Engineer — RTL & Digital IP Design (Intel)
✅ Fresher FriendlyRTL Design
RTL Design SystemVerilog Verilog IP Development ASIC Flows Cadence or Synopsys EDA
Senior Memory Controller Verification Engineer — HBM & GDDR SoC (NVIDIA)
Verification
SystemVerilog UVM Memory Protocols GDDR HBM Python Constrained Random Verification
2026 Campus Hire — Engineer HW, Snapdragon SoC (Qualcomm)
✅ Fresher FriendlyAI Silicon
RTL Design SystemVerilog Verilog VLSI Digital Design ECE Fundamentals
Sr Synthesis & Implementation Engineer — Advanced ASIC SoC (NXP Semiconductors)
Physical Design
Logic Synthesis STA Physical Design Synopsys DC Compiler TCL Scripting RTL Signoff
ASIC DFT Engineer — SoC Test Architecture (Cisco)
DFT
DFT ATPG MBIST Scan Insertion SystemVerilog IEEE 1149.1 SoC Design
Senior FPGA & Emulation Engineer — SoC Pre-Silicon Validation (Scaledge Technology)
FPGA
FPGA Hardware Emulation Xilinx Virtex Synopsys ZeBu SystemVerilog RTL Debugging
SoC Architect — ARM Cortex & RISC-V Platform Design (Texas Instruments India)
SoC Architecture
SoC Architecture ARM Cortex RISC-V Memory Subsystems Power Management RTL PPA Optimization
Senior Principal Engineer — Verification, High-Speed Networking SoC (Marvell Technology)
Verification
SystemVerilog UVM Formal Verification OVM Python SoC Integration Verification
Associate Engineer — DFT, Snapdragon Platform (Qualcomm)
✅ Fresher FriendlyDFT
DFT ATPG JTAG Scan Chain SystemVerilog VLSI Fundamentals
ASIC Physical Design Engineer — RTL-to-GDSII GPU SoC (NVIDIA)
Physical Design
Physical Design RTL-to-GDSII Synthesis STA Cadence Innovus Synopsys ICC2 Floorplanning
Software R&D Engineer — VLSI Physical Design, New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyEDA Tools
C++ Python EDA Tools Physical Design Timing Analysis RTL Scripting Tcl
New College Grad — DRAM Design Engineer, Memory SoC (Micron Technology)
✅ Fresher FriendlyAI Silicon
DRAM Circuit Design Verilog Memory Architecture SPICE Simulation Low Power Design
Senior Pre-Silicon DFT & Design Verification Engineer — SoC Test Architecture (Arm)
DFT
DFT ATPG MBIST JTAG Scan Design SystemVerilog UVM SoC Test Insertion
Silicon Design Engineer — AI Processor & GPU RTL Design, 1-Year Contract (AMD)
AI Silicon
RTL Design Verilog SystemVerilog Digital Circuits Python C++ VLSI Design Flow
Principal Application Engineer — Jasper Formal Verification Platform (Cadence)
EDA Tools
Formal Verification JasperGold SystemVerilog Assertions SVA SoC Security CDC/RDC
Sr. Principal Engineer — RTL ASIC Design, High-Speed Networking SoC (Marvell)
RTL Design
RTL Design SystemVerilog SoC Architecture Logic Synthesis Networking IP Timing Closure
Emulation & FPGA Engineer — SoC Pre-Silicon Prototyping & Validation (NVIDIA)
FPGA
FPGA Emulation Synplify Protocompiler RTL Debugging SystemVerilog Python Palladium
Senior ASIC Timing Engineer — STA & Timing Closure, GPU SoC (NVIDIA)
Physical Design
STA PrimeTime SDC Timing Closure Multi-Corner Analysis ECO Low Power Timing
Staff Design Verification Engineer — SerDes & AMS Mixed-Signal IPs (Marvell)
Verification
SystemVerilog UVM AMS Verification SerDes IP Mixed-Signal SPICE Cadence Xcelium
ASIC Clocks Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
ASIC Clock Design SystemVerilog RTL Design Low Power Design Python GPU Architecture
FPGA Design Engineer — Embedded Systems & Aerospace Applications (Aethrone Aerospace)
✅ Fresher FriendlyFPGA
FPGA Verilog VHDL Xilinx Vivado Embedded Systems Digital Design
PMTS Design Verification Engineer — SoC Focused Constrained Random (Tsavorite Scalable Intelligence)
Verification
SystemVerilog UVM SoC Verification Python Constrained Random Assertions Coverage
SoC Security Engineer — Platform Architecture & Hardware Security (Apple)
SoC Architecture
SoC Security Hardware Security Cryptography RTL Design SystemVerilog Secure Boot
SoC QoS/Fabric Performance Engineer — Platform Architecture (Apple)
SoC Architecture
SoC Fabric Design QoS Architecture NoC Performance Analysis RTL Memory Interconnect
Silicon Engineer, Platform and Devices — University Graduate 2026 (Google)
✅ Fresher FriendlyAI Silicon
VLSI RTL Design SystemVerilog Digital Circuits Python Hardware Verification
VLSI Engineer L3 — RTL & Digital Design Implementation (Wipro)
RTL Design
VLSI Verilog SystemVerilog ASIC Design RTL Logic Design
R&D Engineer — IC Design & ASIC Implementation (Broadcom)
Physical Design
IC Design RTL Design Physical Design ASIC Verilog Timing Analysis
RTL Engineer — Peripherals & Security IP Design (Anthriq)
✅ Fresher FriendlyRTL Design
RTL Design Verilog SystemVerilog Digital Logic FPGA Security IP
Senior ASIC AI Engineer — AI SoC Methodology & RTL Automation (NVIDIA)
AI Silicon
SystemVerilog AI/ML Python ASIC Design RTL Automation LLM
Verification Engineer — ASIC SoC GPU & CPU Verification (NVIDIA)
Verification
SystemVerilog UVM Python Verilog Constrained Random Functional Coverage
Design & Verification Engineer — Entry Level ASIC SoC IP (Core ASIC Inc)
✅ Fresher FriendlyVerification
SystemVerilog UVM Testbench Development ASIC Verification Python
Senior FPGA Engineer — SoC Prototyping & Hardware Emulation (Arm)
FPGA
FPGA Xilinx Intel FPGA SoC Prototyping Hardware Emulation RTL
Physical Design Engineer — RTL to GDSII SoC Digital Implementation (Renesas Electronics)
Physical Design
Physical Design Floorplanning Place & Route STA CTS Calibre Innovus
Staff Package Design Engineer — Advanced IC Packaging & Assembly (Renesas Electronics)
Packaging
IC Package Design Wirebond Flip-Chip BGA Package-on-Package Thermal Analysis
Principal RTL Design Engineer — SoC Digital IP Architecture (STMicroelectronics)
RTL Design
RTL Design Verilog SystemVerilog SoC Architecture Synthesis Formal Verification
SoC Architect — Advanced ARM Cortex System-on-Chip Design (Best NanoTech)
SoC Architecture
SoC Architecture ARM Cortex AMBA AXI Power Management Microarchitecture
SR Engineer ASIC DFT — SoC Test Architecture ATPG & MBIST (Micron Technology)
DFT
DFT ATPG MBIST Scan Insertion Boundary Scan Tessent Synopsys DFT
RTL Design Engineer NOC — Sr Engineer Snapdragon SoC Integration (Qualcomm)
RTL Design
RTL Design Verilog SystemVerilog Network-on-Chip AMBA SoC Integration
Formal Verification Engineer — New College Graduate ASIC SoC (NVIDIA AI)
✅ Fresher FriendlyVerification
Formal Verification SystemVerilog Assertions JasperGold Python
Associate Engineer — IC Design Entry Level ASIC SoC (Silicon Labs)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design Digital Design ASIC Flows
Sr Design Verification Engineer — ASIC/FPGA SoC Platform (Sivaltech)
FPGA
SystemVerilog UVM ASIC/FPGA Python Formal Verification Simulation
ASIC IC Design Engineer — RTL to GDSII Digital Implementation (Globex Digital)
RTL Design
Verilog ASIC Design RTL Synthesis STA IC Implementation
ASIC Verification Engineer — Clock Domain SoC (NVIDIA)
Verification
SystemVerilog UVM RTL Design Verilog Python Clock Domain Crossing
Software Engineer — Hardware Tools & Methodology, New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyEDA Tools
Python RTL Generation EDA Tools Tool Development SystemVerilog Tcl
Full-Chip STA Lead Engineer — SoC Timing Closure (AMD)
Physical Design
STA Primetime Tempus Timing Closure ASIC Implementation Floorplanning
Senior Principal Engineer — Verification, AI Networking SoC (Marvell Technology)
AI Silicon
SystemVerilog UVM SoC Verification Coverage Closure Python Formal
PDK Development Engineer — VLSI Process Design Kit (Texas Instruments)
EDA Tools
PDK SPICE EDA Tools Process Design Kit Calibre Virtuoso
Associate III — DFT & VLSI Design Verification (UST)
✅ Fresher FriendlyDFT
Verilog SystemVerilog UVM DFT ATPG MBIST Tcl
Senior VLSI Engineer — ASIC SoC Architecture & RTL Design (BigEndian Semiconductors)
SoC Architecture
RTL Design SystemVerilog SoC Architecture ASIC Design Synthesis
Design Verification Engineer — Entry Level ASIC/SoC (Zoey Semiconductors)
✅ Fresher FriendlyVerification
SystemVerilog UVM Constrained-Random Coverage Closure Simulation
Design Verification Engineer — UVM SoC IP Testbench (Eximietas Design)
✅ Fresher FriendlyVerification
SystemVerilog UVM Constrained-Random Verification Testbench Development Python
Mixed Signal Design Verification Engineer — AMS SoC & SPICE (Intel)
Verification
SystemVerilog UVM Mixed-Signal DV SPICE Python AMS Verification
Lead Engineer — Design Verification Low Power & UPF SoC (Silicon Labs)
Verification
SystemVerilog UVM UPF CPF Low Power DV SoC Verification Python
Principal Engineer — ASIC Physical Design, Memory SoC (Micron Technology)
Physical Design
Synopsys ICC2 Timing Closure CTS Power Analysis Physical Verification DRAM ASIC
RTL Design Peripheral — Sr Staff Engineer, Snapdragon SoC (Qualcomm)
RTL Design
SystemVerilog Verilog SoC RTL Design Synthesis CDC Low Power Design DFT
SoC Design Verification Engineer — Apple Silicon Platform (Apple)
AI Silicon
SystemVerilog UVM SoC DV Formal Verification Apple Silicon Python
DFT Design Engineer — ATPG, MBIST & SoC Test Architecture (Sykatiya Technologies)
DFT
DFT ATPG MBIST Tessent Synopsys DFT Compiler Scan Insertion SoC Test
SoC Verification Manager/Lead — GPU & AI Chiplet Verification (AMD)
SoC Architecture
SystemVerilog UVM SoC Verification Python Emulation Formal Verification
VLSI Physical Design Intern — RTL-to-GDSII EDA Flow (Cadence Design Systems)
✅ Fresher FriendlyEDA Tools
Physical Design Floor Planning P&R CTS Synthesis Cadence Innovus Tempus
Cell Modeling and Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
Verilog SystemVerilog Cell Library Verification Python Spice ASIC DFT
SoC Verification Manager/Lead — GPU & AI Chiplet Verification (AMD)
SoC Architecture
SystemVerilog UVM SoC Verification Python Emulation Formal Verification
VLSI Physical Design Intern — RTL-to-GDSII EDA Flow (Cadence Design Systems)
✅ Fresher FriendlyEDA Tools
Physical Design Floor Planning P&R CTS Synthesis Cadence Innovus Tempus
Design Verification Engineer — UVM SoC IP Testbench (Eximietas Design)
✅ Fresher FriendlyVerification
SystemVerilog UVM Constrained-Random Verification Testbench Development Python
Cell Modeling and Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
Verilog SystemVerilog Cell Library Verification Python Spice ASIC DFT
Mixed Signal Design Verification Engineer — AMS SoC & SPICE (Intel)
Verification
SystemVerilog UVM Mixed-Signal DV SPICE Python AMS Verification
Lead Engineer — Design Verification Low Power & UPF SoC (Silicon Labs)
Verification
SystemVerilog UVM UPF CPF Low Power DV SoC Verification Python
Principal Engineer — ASIC Physical Design, Memory SoC (Micron Technology)
Physical Design
Synopsys ICC2 Timing Closure CTS Power Analysis Physical Verification DRAM ASIC
RTL Design Peripheral — Sr Staff Engineer, Snapdragon SoC (Qualcomm)
RTL Design
SystemVerilog Verilog SoC RTL Design Synthesis CDC Low Power Design DFT
SoC Design Verification Engineer — Apple Silicon Platform (Apple)
AI Silicon
SystemVerilog UVM SoC DV Formal Verification Apple Silicon Python
DFT Design Engineer — ATPG, MBIST & SoC Test Architecture (Sykatiya Technologies)
DFT
DFT ATPG MBIST Tessent Synopsys DFT Compiler Scan Insertion SoC Test
Infra Design Verification Engineer — Hardware SoC Verification (Qualcomm)
Verification
SystemVerilog UVM ASIC Verification SoC Digital Design Python
Memory Circuit Design Engineer — High-Speed SRAM & DRAM IP (Broadcom)
RTL Design
Memory Design SRAM Circuit Design SPICE Custom Layout Analog IC
Package Layout Design Senior Staff Engineer — Advanced IC Packaging (Marvell)
Packaging
IC Package Design High-Speed Signal Integrity Cadence APD 2.5D/3D Packaging BGA
FPGA Senior Design Engineer — Embedded Systems & IP Integration (Microchip Technology)
FPGA
FPGA VHDL Verilog Xilinx Vivado Timing Closure Embedded Systems
ASIC Design Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM RTL Verification Python ASIC Design
Hardware Design Engineering Intern/Co-Op — ASIC Physical Design 2026 (AMD)
✅ Fresher FriendlyPhysical Design
Physical Design ASIC Verification Memory Interface Simulation VLSI Design Flow
Associate II VLSI — Verilog & UVM Design Verification (UST)
✅ Fresher FriendlyVerification
Verilog SystemVerilog UVM Digital Design Memory IP
Principal Physical Design Engineer — Advanced SoC Implementation (NXP Semiconductors)
Physical Design
Physical Design Place & Route Timing Closure STA Floor Planning CTS
Staff DFT Engineer — Edge AI Silicon Test Architecture (EnCharge AI)
DFT
DFT ATPG MBIST Scan Insertion JTAG Test Architecture
SoC Design and Integration Engineer — Apple Silicon (Apple)
SoC Architecture
SoC Integration RTL Design Verilog Synthesis Timing Analysis Floor Planning
CPU & GPU Architecture Software Engineer — ATG Group (Arm)
SoC Architecture
ARM Architecture CPU Design SystemVerilog C++ Python SoC Integration
Design Verification Engineer — SoC IP & Constrained-Random (TYLsemi)
✅ Fresher FriendlyVerification
SystemVerilog UVM SVA Constrained-Random Verification Python
Test & Tools Development Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyDFT
DFT Python Automation Simulation Debug Test Development RTL
VLSI Engineer I — Entry Level Server & ASIC Architecture (HPE)
✅ Fresher FriendlyRTL Design
RTL Design Verilog SystemVerilog Digital Design ASIC Methodology
SMTS Verification IP Engineer — EDA Tools & Protocol Simulation (Siemens EDA)
EDA Tools
SystemVerilog UVM Python Protocol VIP EDA Tools Simulation
ASIC RTL Design Engineer — AI SoC & Dojo Silicon (Tesla)
AI Silicon
SystemVerilog RTL Design Verilog STA Synthesis Microarchitecture
Design Verification Engineer — Silicon & Systems Group (Amazon Lab126)
Verification
SystemVerilog UVM Functional Verification SoC C++ Python
Senior ASIC RTL Engineer — Silicon & CPU Design (Google)
RTL Design
SystemVerilog RTL Design Logic Synthesis Low-Power Design Timing Analysis
Physical Design Engineer — ASIC RTL to GDSII Implementation (TCS)
Physical Design
Physical Design Floorplanning P&R STA Synopsys ICC2 Cadence Innovus
FPGA Design Engineer — System Design & IP Integration (UST)
FPGA
FPGA Verilog VHDL Xilinx Vivado IP Integration Timing Closure AXI
DFT Engineer — SoC Test Strategy, ATPG & MBIST (Nsemi Design Services)
DFT
DFT ATPG MBIST Scan Insertion Boundary Scan SoC Test Architecture BIST
SoC Architect — ARM Cortex Systems & Strategic Product Definition (Texas Instruments)
SoC Architecture
SoC Architecture ARM Cortex System Architecture Digital Design Performance Modeling RTL
NPU Design Verification Associate Engineer — AI Processor Verification (Qualcomm)
AI Silicon
SystemVerilog UVM NPU Verification Python Processor Architecture AI Chip
Design Verification Engineer — Complex ASIC/SoC & IP Validation (HCL Tech)
Verification
SystemVerilog UVM ASIC Verification SoC IP Verification Scripting
Lead RTL Verification Engineer — EDA Tools & VCS Regression (Synopsys)
EDA Tools
SystemVerilog UVM VCS Questa EDA Tools TCL Python RTL Verification
FPGA/EDA Flows Automation Engineer — Agentic AI & Python Scripting (AMD)
FPGA
FPGA EDA Flows Python Agentic AI Automation Bash Scripting ASIC Design Flow
Staff ASIC Physical Design Engineer — DRAM & Memory SoC Implementation (Micron Technology)
Physical Design
Physical Design Place & Route STA Power Analysis Synthesis Floorplanning ICC2
VLSI Design and Development Engineer — RTL & Digital Circuits (Nxfee Innovation)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design Digital Design FPGA ModelSim
VLSI/Embedded Engineer — Digital Design & FPGA (ChipSol Private Limited)
✅ Fresher FriendlyFPGA
Verilog FPGA Embedded Systems Digital Design SystemVerilog
ASIC Physical Design Engineer, Netlisting — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Physical Design Logic Equivalence Checking Formal Verification Synthesis RTL GDSII
Mixed-Signal Verification Engineer — RF & AMS SoC IP (Apple)
Verification
Mixed-Signal Verification SystemVerilog AMS RF Verification SPICE MATLAB UVM
Hardware Technologies Masters Engineering Intern — SoC Silicon Design (Apple)
✅ Fresher FriendlySoC Architecture
RTL Design VLSI Computer Architecture Python SystemVerilog ASIC Design Flow Verification
Senior DFT Engineer — SoC Test Architecture & ATPG (MosChip)
DFT
DFT ATPG Scan Insertion JTAG Boundary Scan Tessent Synopsys DFT Compiler MBIST
Sr Staff Engineer — RTL Design NOC & Snapdragon SoC Architecture (Qualcomm)
SoC Architecture
RTL Design Verilog SystemVerilog NoC Architecture Low Power Design Logic Synthesis Formal Verification
Silicon Design Engineer 1 — Entry Level GPU & AI SoC Digital Design (AMD)
✅ Fresher FriendlyAI Silicon
RTL Design Verilog SystemVerilog Digital Design Python Logic Synthesis ASIC Flow
Senior Physical Design Engineer — ASIC Timing Closure & STA (Lyptus Technologies)
Physical Design
Physical Design Place & Route Static Timing Analysis CTS IR Drop Cadence Innovus Synopsys PrimeTime
ASIC Design Engineer — New College Graduate 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
RTL Design Verilog SystemVerilog ASIC Design Flow Logic Synthesis Timing Analysis Python
Senior/Staff Design Verification Engineer — RISC-V SoC IP (SiFive)
Verification
SystemVerilog UVM RISC-V SoC Verification Functional Coverage Constrained Random Python
Physical Design Lead — Full Chip & Chiplet SoC Integration (AMD)
Physical Design
Physical Design Timing Closure STA Power Grid Chiplet Integration Cadence Innovus Synopsys ICC2
Senior Staff Engineer — RTL Design & SoC Integration (Marvell Technology)
RTL Design
RTL Design SystemVerilog SoC Integration Low Power Design Logic Synthesis CDC Analysis Formal Verification
Hardware Technologies Undergrad Engineering Intern — SoC Silicon (Apple India)
✅ Fresher FriendlySoC Architecture
VLSI Design SoC Architecture Verilog Computer Architecture Python
SoC RTL Design Engineer — Next-Gen Platform Silicon (Intel India)
RTL Design
RTL Design SystemVerilog SoC Integration Low Power Design UPF
Sr. DFT Engineer — Complex SoC Test Architecture & ATPG (NXP Semiconductors)
DFT
DFT Architecture ATPG MBIST Scan Insertion JTAG SystemVerilog
Physical Design Engineer — FPGA & ASIC Timing Closure (Altera)
Physical Design
Physical Design Clock Tree Synthesis Timing Closure PnR STA Coverage Analysis
Analog Design Engineer — Entry Level Mixed-Signal IC (Texas Instruments India)
✅ Fresher FriendlyAnalog Design
Analog Design Verilog SPICE Mixed-Signal Transistor-Level Design
Senior Principal RTL Design Engineer — EDA & Chip Design Tools (Cadence)
✅ Fresher FriendlyEDA Tools
RTL Design SystemVerilog EDA Tool Flow Synthesis CDC/RDC Timing
RTL Designer — Automotive ASIC with FUSA & ASIL Compliance (Mulya Technologies)
RTL Design
RTL Design SystemVerilog FUSA ASIL Automotive IP Micro-architecture
Design Verification Engineer — Entry Level SoC & IP DV (Galaxy i Technologies)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verilog Functional Verification Simulation
ASIC Verification Engineer — GPU & AI SoC IP Verification (NVIDIA)
Verification
SystemVerilog UVM Python RTL Verification Coverage Closure
Senior Digital Design Engineer — AI GPU & Next-Gen SoC RTL (NVIDIA)
AI Silicon
RTL Design SystemVerilog Synthesis Timing Analysis Micro-architecture
Software Engineer II — EDA Tools & Chip Design Automation (Cadence)
✅ Fresher FriendlyEDA Tools
C++ EDA SystemVerilog Python Virtuoso MIPI Software Development
ASIC RTL Design Engineer — Entry Level PCIe & SoC IP (xQWave Technologies)
✅ Fresher FriendlyRTL Design
RTL Design Verilog SystemVerilog PCIe ASIC Simulation Synthesis
Power Methodology and Modeling Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyAI Silicon
RTL Design Power Analysis Machine Learning Python Chip Design Flow
Mixed Signal Design Verification Engineer — AMS & VLSI SoC (Intel)
Verification
Mixed Signal Verification SystemVerilog UVM SPICE Analog IP SoC
AI SoC Design Engineer — Next-Gen Data Center Silicon (Intel)
AI Silicon
RTL Design SoC Architecture AI Accelerator Logic Synthesis Timing Closure
Design Verification Staff Engineer — IP & SoC Functional DV (Qualcomm)
Verification
SystemVerilog UVM Functional Coverage Formal Verification SoC DV
DFT Engineer — High-Speed Automotive SerDes SoCs (Texas Instruments)
DFT
DFT ATPG Scan Insertion BIST SerDes Automotive SoC Tessent
R&D Staff Engineer — EDA Tools & Algorithms (Synopsys)
EDA Tools
EDA Tools C++ Python Algorithms RTL Synthesis Static Timing Analysis
Sr. Engineer — ASIC Physical Design & DFT (Ayar Labs Photonics)
Physical Design
Physical Design Floorplanning Timing Closure DFT ATPG ASIC Sign-off Photonics
FPGA Prototyping & Emulation Developer SMTS — Memory SoC (Micron Technology)
FPGA
FPGA Xilinx Versal UltraScale RTL HAPS Emulation SoC Pre-Silicon
Silicon SoC Architect — Next-Gen Client & Server Chips (Intel)
SoC Architecture
SoC Architecture ARM Cortex PCIe DDR Power Management Digital Design Micro-Architecture
GPU Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM Python GPU Architecture Functional Verification
DFT Silicon Design Engineer — GPU & AI Chips (AMD)
DFT
DFT ATPG Scan Insertion JTAG Boundary Scan Mentor Tessent
CPU Design Verification Engineer — High-Performance & Low Power (Qualcomm)
Verification
SystemVerilog UVM CPU Architecture Low Power Verification Python
Principal Engineer — Physical Design Full-Chip Implementation (Analog Devices)
Physical Design
Physical Design Floorplanning Place & Route Timing Closure Cadence Innovus Power Analysis
AI Platform Architect — XPU & HPC Silicon Design (TylSemi)
AI Silicon
SoC Architecture AI Accelerators NoC Design RISC-V HPC RTL Design
Systems Architecture Intern — VLSI SoC & EDA Flow (STMicroelectronics)
✅ Fresher FriendlySoC Architecture
VLSI Design EDA Tools RTL Design Physical Design Flow Python SPICE
Design Intern — RISC-V Processor & Digital RTL (InCore Semiconductors)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog Digital Design RISC-V Computer Architecture Python
DSP FPGA Engineer — Timing Closure & Signal Processing (SpaceRelays)
FPGA
FPGA Xilinx DSP Algorithms RTL VHDL Verilog Vivado Signal Processing
Design Verification Engineer — Silicon & AI SoC (Google)
Verification
SystemVerilog UVM C++ Python SoC Verification Coverage-Driven Verification
Design Intern — RISC-V Processor & Digital RTL (InCore Semiconductors)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog Digital Design RISC-V Computer Architecture Python
DSP FPGA Engineer — Timing Closure & Signal Processing (SpaceRelays)
FPGA
FPGA Xilinx DSP Algorithms RTL VHDL Verilog Vivado Signal Processing
Silicon SoC Architect — Next-Gen Client & Server Chips (Intel)
SoC Architecture
SoC Architecture ARM Cortex PCIe DDR Power Management Digital Design Micro-Architecture
Design Verification Engineer — Silicon & AI SoC (Google)
Verification
SystemVerilog UVM C++ Python SoC Verification Coverage-Driven Verification
GPU Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM Python GPU Architecture Functional Verification
DFT Silicon Design Engineer — GPU & AI Chips (AMD)
DFT
DFT ATPG Scan Insertion JTAG Boundary Scan Mentor Tessent
CPU Design Verification Engineer — High-Performance & Low Power (Qualcomm)
Verification
SystemVerilog UVM CPU Architecture Low Power Verification Python
Principal Engineer — Physical Design Full-Chip Implementation (Analog Devices)
Physical Design
Physical Design Floorplanning Place & Route Timing Closure Cadence Innovus Power Analysis
AI Platform Architect — XPU & HPC Silicon Design (TylSemi)
AI Silicon
SoC Architecture AI Accelerators NoC Design RISC-V HPC RTL Design
Systems Architecture Intern — VLSI SoC & EDA Flow (STMicroelectronics)
✅ Fresher FriendlySoC Architecture
VLSI Design EDA Tools RTL Design Physical Design Flow Python SPICE
Lead Engineer — Design Verification Low Power & UPF (Silicon Labs)
Verification
SystemVerilog UVM Low Power Verification UPF CPF CDC
Staff Engineer — ASIC Design Verification NAND DDR PCIe (Micron Technology)
Verification
SystemVerilog UVM NAND Verification DDR PCIe ASIC Simulation
R&D Engineer — IC Design & Memory Validation (Broadcom)
Physical Design
Memory Design IC Validation VLSI SRAM Circuit Design Simulation
DFT Design Engineer — RTL Coding ATPG & Test Content (Intel)
DFT
DFT RTL ATPG Scan Insertion Logic Design Timing Closure
VLSI Engineer L2 — Digital Design RTL & Physical Flow (Wipro)
RTL Design
VLSI Design RTL Physical Design SystemVerilog Digital Circuits
Staff Design Verification Engineer — SerDes & AMS Mixed-Signal IPs (Marvell Technology)
Verification
SerDes AMS Mixed-Signal Verification SystemVerilog UVM Photonics
RTL Design Lead — Complex ASIC & SoC Architecture (Dasro Consulting)
RTL Design
RTL Design ASIC SoC Architecture SystemVerilog Verilog FPGA
Design Verification Engineer — Entry Level VLSI & Functional Simulation (Siliconnect Labs)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verilog VLSI Fundamentals Functional Simulation
Analog Layout Engineer — Entry Level Analog & RF IC Design (Modernize Chip Solutions)
✅ Fresher FriendlyPhysical Design
Analog Layout Cadence Virtuoso RF Circuits VLSI Mixed-Signal IC
VLSI Design Engineer — M.Tech Fresher RTL & Digital ASIC Design (ACL Digital)
✅ Fresher FriendlyRTL Design
RTL Design SystemVerilog Verilog VLSI Digital Design M.Tech
VLSI Engineer L2 — Digital Design RTL & Physical Flow (Wipro)
RTL Design
VLSI Design RTL Physical Design SystemVerilog Digital Circuits
Staff Design Verification Engineer — SerDes & AMS Mixed-Signal IPs (Marvell Technology)
Verification
SerDes AMS Mixed-Signal Verification SystemVerilog UVM Photonics
RTL Design Lead — Complex ASIC & SoC Architecture (Dasro Consulting)
RTL Design
RTL Design ASIC SoC Architecture SystemVerilog Verilog FPGA
VLSI Design Engineer — M.Tech Fresher RTL & Digital ASIC Design (ACL Digital)
✅ Fresher FriendlyRTL Design
RTL Design SystemVerilog Verilog VLSI Digital Design M.Tech
Lead Engineer — Design Verification Low Power & UPF (Silicon Labs)
Verification
SystemVerilog UVM Low Power Verification UPF CPF CDC
Staff Engineer — ASIC Design Verification NAND DDR PCIe (Micron Technology)
Verification
SystemVerilog UVM NAND Verification DDR PCIe ASIC Simulation
R&D Engineer — IC Design & Memory Validation (Broadcom)
Physical Design
Memory Design IC Validation VLSI SRAM Circuit Design Simulation
DFT Design Engineer — RTL Coding ATPG & Test Content (Intel)
DFT
DFT RTL ATPG Scan Insertion Logic Design Timing Closure
Design Verification Engineer — Entry Level VLSI & Functional Simulation (Siliconnect Labs)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verilog VLSI Fundamentals Functional Simulation
Analog Layout Engineer — Entry Level Analog & RF IC Design (Modernize Chip Solutions)
✅ Fresher FriendlyPhysical Design
Analog Layout Cadence Virtuoso RF Circuits VLSI Mixed-Signal IC
ASIC Front End Design Engineer — Entry Level RTL & Logic Design (Symansys Technologies)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design Logic Synthesis ASIC Flow
RTL Design Senior Engineer — Snapdragon SoC Digital Frontend (Qualcomm)
RTL Design
RTL Design SystemVerilog Verilog Logic Design Synthesis
Functional Safety Systems Senior Staff Engineer — ASIL SoC Arch (Qualcomm)
SoC Architecture
Functional Safety ISO 26262 SoC Architecture ASIL FMEA
Lead Physical Design Engineer — AI NPU Advanced Node (NXP Semiconductors)
Physical Design
Physical Design Floorplan Place & Route STA AI NPU FinFET
Deep Learning Engineer — AI Chip & Embedded ML (STMicroelectronics)
AI Silicon
Deep Learning TensorFlow PyTorch Embedded ML C/C++ ONNX
Digital Design Engineer — Entry Level ASIC RTL & CXL/NVMe IP (Chiplogic Technologies)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design CXL NVMe EDA Tools
Staff Physical Design Engineer — Implementation Flow & Methodology (Synopsys)
EDA Tools
Physical Design ICC2 Fusion Compiler STA Low Power FinFET
Lead EDA Software Development Engineer — CAD & Design Automation (AMD)
EDA Tools
C++ Python EDA Tools Tcl Perl Design Automation VLSI CAD
Design Verification Engineer — SoC/IP Power Management Entry Level (Ampere)
✅ Fresher FriendlyVerification
SystemVerilog UVM Power Management SoC Verification Verilog
ASIC Verification Engineer — IP & Cluster RTL Verification (NVIDIA)
Verification
SystemVerilog UVM RTL Verification Python ASIC Debug
Design Verification Engineer — Entry Level VLSI & Functional Verification (AndGate Informatics)
✅ Fresher FriendlyVerification
SystemVerilog UVM Testbench Development Functional Coverage Python
Design Verification Engineer — Silicon & Systems Group (Amazon Lab126)
Verification
SystemVerilog UVM SoC DV AMBA Protocols Formal Verification
Senior DFT Engineer — Complex SoC Test Architecture (NXP Semiconductors)
DFT
DFT Architecture ATPG JTAG Boundary Scan Synopsys TestMAX
Principal Engineer — ASIC Development Engineering RTL Design (Sandisk)
RTL Design
RTL Design SystemVerilog ASIC Design Flow Low Power Design SoC Integration
FPGA Circuit Design Engineer — High-Performance ASIC & FPGA Prototyping (Altera)
FPGA
FPGA Design CMOS Circuit Design RTL Timing Closure Quartus Prime
Member Technical Staff — EDA Software Engineering (Siemens EDA)
EDA Tools
EDA Tools C++ Python VLSI Design Flow Calibre Digital Simulation
Senior Physical Design Engineer — Full SoC Implementation Flow (eInfochips)
Physical Design
Physical Design Floorplanning CTS Routing STA Synthesis DFM
ASIC RTL Design Engineer — SoC Architecture & Interface IP (Semi Leaf)
SoC Architecture
RTL Design SystemVerilog SoC Integration PCIe AXI Low Power Techniques
Design Verification Engineer — Entry Level SoC & IP Verification (Interex Semiconductor)
✅ Fresher FriendlyVerification
SystemVerilog UVM SV Assertions Functional Coverage Simulation
ASIC RTL Design Engineer — Entry Level Digital Design (Sauvira Solutions)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design ASIC Synthesis Linting
VLSI & Semiconductor Design Engineer — Multiple Roles incl. Fresher (DynPro India)
✅ Fresher FriendlyVerification
VLSI Design RTL Physical Design Verification DFT SoC
Senior FPGA Engineer — Xilinx/AMD Devices & RTL Design (ARM)
FPGA
FPGA Design Xilinx/AMD Devices Vivado SystemVerilog RTL Tcl Scripting
GPU Design Verification Engineer — SoC & AI Chip DV (MediaTek)
Verification
SystemVerilog UVM GPU Verification SoC Debug Python Coverage-Driven DV
Design Verification Engineer — IP & Subsystem SoC DV (ElevarSoC Technologies)
Verification
SystemVerilog UVM SoC Verification Functional Coverage SVA Assertions
Senior Engineer — Digital Design & DFT (Analog Devices)
DFT
DFT Scan Insertion ATPG BIST SoC Test Architecture Fault Simulation
Lead FPGA Design Engineer — Complex Systems Architecture (Avia Technologies)
FPGA
FPGA Architecture VHDL Verilog RTL Design System-Level Integration Verification
FPGA Prototyping Platform SMTS — SoC Pre-Silicon Emulation (Tsavorite Scalable Intelligence)
SoC Architecture
FPGA Prototyping Python Tcl Intel Altera/Xilinx FPGAs SoC Emulation SystemVerilog
Senior Design Verification Engineer — SystemVerilog UVM SoC (Scaledge Technology)
Verification
SystemVerilog UVM SoC Verification Assertions Coverage Formal Verification
SOC Verification Graduate Intern — AI Hardware Pre-Silicon (Tesla)
✅ Fresher FriendlyAI Silicon
SystemVerilog UVM RTL Verification Python SoC Pre-Silicon Simulation
VLSI Design Engineer — Entry Level RTL & Verification Roles (VLSI FOR ALL)
✅ Fresher FriendlyRTL Design
RTL Design Verilog SystemVerilog ASIC Design Flow Digital Logic
GPU Design Verification Engineer — SoC & AI Chip DV (MediaTek)
Verification
SystemVerilog UVM GPU Verification SoC Debug Python Coverage-Driven DV
Design Verification Engineer — IP & Subsystem SoC DV (ElevarSoC Technologies)
Verification
SystemVerilog UVM SoC Verification Functional Coverage SVA Assertions
Senior Engineer — Digital Design & DFT (Analog Devices)
DFT
DFT Scan Insertion ATPG BIST SoC Test Architecture Fault Simulation
Lead FPGA Design Engineer — Complex Systems Architecture (Avia Technologies)
FPGA
FPGA Architecture VHDL Verilog RTL Design System-Level Integration Verification
FPGA Prototyping Platform SMTS — SoC Pre-Silicon Emulation (Tsavorite Scalable Intelligence)
SoC Architecture
FPGA Prototyping Python Tcl Intel Altera/Xilinx FPGAs SoC Emulation SystemVerilog
Senior Design Verification Engineer — SystemVerilog UVM SoC (Scaledge Technology)
Verification
SystemVerilog UVM SoC Verification Assertions Coverage Formal Verification
SOC Verification Graduate Intern — AI Hardware Pre-Silicon (Tesla)
✅ Fresher FriendlyAI Silicon
SystemVerilog UVM RTL Verification Python SoC Pre-Silicon Simulation
VLSI Design Engineer — Entry Level RTL & Verification Roles (VLSI FOR ALL)
✅ Fresher FriendlyRTL Design
RTL Design Verilog SystemVerilog ASIC Design Flow Digital Logic
VLSI & Semiconductor Design Engineer — Multiple Roles incl. Fresher (DynPro India)
✅ Fresher FriendlyVerification
VLSI Design RTL Physical Design Verification DFT SoC
Senior FPGA Engineer — Xilinx/AMD Devices & RTL Design (ARM)
FPGA
FPGA Design Xilinx/AMD Devices Vivado SystemVerilog RTL Tcl Scripting
VLSI Design Engineer — DV, Physical Design & RTL Multiple Roles (LanceSoft)
Verification
VLSI Design RTL SystemVerilog UVM Physical Design STA DFT Circuit Design
DFT Engineer — Entry Level ASIC Test Design (Sivaltech)
✅ Fresher FriendlyDFT
DFT SCAN MBIST BSCAN ATPG TestMAX Verilog
Memory Layout Engineer — Entry Level VLSI Backend (Ishva Semiconductors)
✅ Fresher FriendlyPhysical Design
Memory Layout Cadence Virtuoso GDSII DRC LVS SRAM Custom Layout
DFT Engineer — Entry Level Test Architecture (Texas Instruments India)
✅ Fresher FriendlyDFT
DFT SCAN Insertion BIST ATPG Test Compression DFT Architecture Verilog
Senior Physical Design Engineer — Advanced Node SoC (Samsung Semiconductor)
Physical Design
Physical Design Floorplan CTS STA P&R Synopsys ICC2 Advanced Node Low Power
Senior SoC Logic Design Engineer — ARM-Based Chip Integration (IBM India)
SoC Architecture
SoC Integration ARM Cortex RTL Design SystemVerilog Synthesis UPF Power Management
Senior RTL/FPGA Design Engineer — Avionics & Space Systems (Azista Space)
FPGA
RTL Design FPGA VHDL SystemVerilog Xilinx/Intel FPGA Vivado Avionics Space Systems
Design Verification Engineer — IP & Subsystem DV (AMD)
Verification
SystemVerilog UVM Formal Verification IP Verification Python Functional Coverage
Physical Design Manager — Advanced Node SoC Leadership (insemi Technology Services)
Physical Design
Physical Design SoC Floorplan CTS STA Advanced Node Below 14nm Low Power Team Leadership
FPGA/RTL Design Engineer — SoC Prototyping & Emulation (ApexPlus Technologies)
FPGA
FPGA RTL Design Verilog VHDL Xilinx/Altera Vivado Simulation SoC Prototyping
Design Verification Engineer — ASIC & UVM (Eximietas Design)
✅ Fresher FriendlyVerification
SystemVerilog UVM ASIC Verification Testbench Debugging
ASIC SoC RTL Design Engineer — Digital Design (Eximietas Design)
RTL Design
Verilog RTL Coding SoC Design Digital Logic Synthesis
Design Verification Engineer (Internship) — VLSI & UVM Fundamentals (EdgeSilica)
✅ Fresher FriendlyVerification
SystemVerilog UVM Basics Testbench Development Verilog
Senior ASIC RTL Integration Engineer — High-Speed GPU Design (NVIDIA)
RTL Design
Verilog SystemVerilog RTL Synthesis Design Integration GPU Architecture
Senior Chip Design Verification Engineer — ASIC Frontend (NVIDIA)
Verification
SystemVerilog UVM RTL Verification Formal Methods Debugging
ASIC Chip Design Verification Engineer — Entry Level (NVIDIA)
✅ Fresher FriendlyVerification
Verilog SystemVerilog UVM Basics Testbench Development Debugging
Hardware System Engineer — iPhone SoC Architecture (Apple)
SoC Architecture
SoC Architecture Verilog SystemVerilog Hardware Design Power Management
SoC Design Verification Engineer — Pre-Silicon Validation (Apple)
Verification
UVM SystemVerilog SoC Verification RTL Design Scripting (Python/Perl)
SoC RTL Design — Staff Engineer (Qualcomm)
RTL Design
Verilog SystemVerilog RTL Design SoC Integration Design Methodology
Infra DV Staff Engineer — Verification & Bus Protocols (Qualcomm)
Verification
UVM SystemVerilog ARM Bus Protocols Formal Verification Debugging
Design Verification Engineer — Entry Level DV & UVM (SocBridge Semiconductors)
✅ Fresher FriendlyVerification
SystemVerilog UVM Functional Verification Verilog AMBA Protocols Simulation
VLSI Design Engineer — Multiple Roles | DV, PD, DFT, RTL (SiSoC Semiconductor)
✅ Fresher FriendlyVerification
SystemVerilog UVM Physical Design DFT RTL Design SoC Verification Innovus
ASIC Physical Design Engineer — Junior & Senior ASIC Backend Flow (NVIDIA)
Physical Design
Physical Design Synthesis Formal Verification STA Python Perl GDSII
Senior Engineer — Physical Design & Methodology (Marvell Technology)
Physical Design
Physical Design PnR STA CTS ECO Synthesis Low-Power Techniques
IP and Subsystem Verification Engineer — Pre-Silicon SoC (Intel)
Verification
SystemVerilog UVM Pre-Silicon Verification SoC Architecture Python AMBA
IP Design Engineer — RTL, SoC & Embedded Processors (Texas Instruments)
RTL Design
RTL Design Verilog SystemVerilog SoC Integration Embedded Processors Synthesis
LEC CAD Engineer — Staff Equivalence Checking & EDA Flow (Qualcomm)
EDA Tools
LEC Formal Equivalence Checking Cadence Conformal EDA Tools TCL Scripting CAD Automation
Senior Principal Engineer — VLSI DFT & Test Logic (Mulya Technologies)
DFT
DFT ATPG JTAG Scan Insertion MBIST Boundary Scan Tessent Synopsys DFT
Staff Physical Design Engineer — AI Chip Floorplan & PDN (enCharge AI)
AI Silicon
Physical Design Floorplanning PDN Analysis EM/IR AI SoC Advanced Node Innovus ICC2
Physical Design Engineer — Entry Level ASIC Backend Flow (Chiplogic Technologies)
✅ Fresher FriendlyPhysical Design
Physical Design Verilog STA Floorplanning CTS PnR Cadence Innovus
SOC Design Engineer — RTL Integration & Chip Frontend (NVIDIA)
SoC Architecture
RTL Design SystemVerilog SoC Integration Padring Pinmux UPF
CPU Design Verification Engineer — Snapdragon Power Management (Qualcomm)
Verification
SystemVerilog UVM Power Management Verification CPU Architecture SoC DV
Analog Design Engineer — Mixed-Signal SoC Wireless Infrastructure (Texas Instruments)
SoC Architecture
Analog Design Mixed-Signal SoC Wireless Infrastructure SPICE Cadence Virtuoso
Senior/Staff Design Verification Engineer — FPGA DV (Lattice Semiconductor)
Verification
SystemVerilog UVM Design Verification FPGA Formal Verification Coverage
Principal Engineer — EDA Embedded Firmware & FPGA (Synopsys)
EDA Tools
FPGA Embedded Firmware EDA Tools C/C++ SystemVerilog Embedded C
Lead Software Engineer — EDA HDL Verification Tools (Cadence)
EDA Tools
Verilog VHDL EDA Tools C++ SystemVerilog Software Development
Staff Memory Circuit Design Verification Engineer — DRAM & SRAM (Micron Technology)
Verification
SRAM DRAM Memory Circuit Verification SystemVerilog UVM Custom Layout
RTL Design Engineer — Entry Level Digital Design (IndieSemiC)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design Digital Electronics FPGA CMOS
Early Career SoC DFT Verification Engineer — m/f/d (Apple)
✅ Fresher FriendlyDFT
DFT ATPG Scan Insertion SystemVerilog Python BIST
DFT Engineer — Entry Level ASIC Test Design (Tattvasemi Technologies)
✅ Fresher FriendlyDFT
DFT ATPG Scan Chain Boundary Scan JTAG SystemVerilog
Coherency Design Verification Engineer — CHI Multicore CPU (7Rays Semiconductors)
Verification
SystemVerilog UVM CHI Protocol Coherency Verification CPU Verification Coverage
FPGA Developer — Internship + Full-Time (Vicharak)
✅ Fresher FriendlyFPGA
FPGA Verilog VHDL Digital Design RISC-V Hardware Description Language
Associate VLSI DFT Engineer — Test Methodologies (UST)
✅ Fresher FriendlyDFT
DFT Scan Insertion ATPG BIST Test Coverage Analysis VLSI
DFT Engineer — Next-Gen Chip Architecture (Mettlesemi Systems)
✅ Fresher FriendlyDFT
DFT ATPG Scan Chains Boundary Scan Clock Gating Test Architecture
Senior Logic Design Engineer — GPU ASIC RTL (NVIDIA)
RTL Design
SystemVerilog Verilog RTL Design ASIC Synthesis Timing Closure Logic Design
Formal Verification Engineer — ASIC Design (NVIDIA India)
Verification
Formal Verification JasperGold Questa Formal SystemVerilog ASIC Property Checking
Senior Lead Physical Design Engineer — Snapdragon SoC (Qualcomm)
Physical Design
Physical Design STA CTS Place & Route PrimeTime Snapdragon Advanced Node
DFT Engineer — Snapdragon ASIC Test Architecture (Qualcomm)
DFT
DFT ATPG Scan Insertion BIST JTAG Test Coverage Boundary Scan
FPGA Prototyping Design Engineer — SoC Integration (Apple)
FPGA
FPGA SoC Prototyping Hardware IP Integration Synthesis Place & Route Emulation
RTL Design Engineer — Chiplet Interconnect Technology (AMD)
RTL Design
RTL Design Verilog SystemVerilog Chiplet Interconnect DFT VLSI Synthesis
DFT Engineer — Snapdragon ASIC Silicon (Qualcomm)
DFT
DFT ATPG Scan Insertion BIST MBIST Silicon Debug Qualcomm ASIC
Design Verification Engineer — Google Cloud Silicon TPU (Google)
Verification
SystemVerilog UVM Python Functional Coverage RTL Verification Google Cloud AI
SoC & FPGA Performance Architect — System Modeling (Altera)
FPGA
FPGA Architecture SoC Performance Modeling SystemVerilog C++ Simulation Power Analysis
Principal SoC RTL Design Engineer — High-Speed Interfaces (TylSemi)
RTL Design
RTL Design SystemVerilog SoC Integration PCIe AXI Micro-Architecture Synthesis
Design Verification Engineer — VLSI Semiconductor (Capgemini Engineering)
Verification
SystemVerilog UVM Constraint Random Verification Functional Coverage Semiconductor IP
Silicon Engineer — Platform & Devices, University Graduate 2026 (Google)
✅ Fresher FriendlyAI Silicon
SystemVerilog RTL Design Hardware Verification SoC Python Digital Logic
Software Engineering Intern — EDA Tools & Platform (Synopsys)
✅ Fresher FriendlyEDA Tools
C++ Python EDA Tools Software Development Data Structures Algorithms
Analog Layout Trainee — Semiconductor Design (Digicomm Semiconductor)
✅ Fresher FriendlyPhysical Design
Analog Layout Cadence Virtuoso Custom IC Layout LVS DRC Schematic Reading
Senior DFT Engineer — Complex SoC Test Architecture (NXP Semiconductors)
DFT
DFT ATPG Scan Chain JTAG Boundary Scan SoC Test Architecture Mentor TestKompress
Lead Physical Design Engineer — SoC Implementation & Synthesis (Texas Instruments)
Physical Design
Physical Design Synopsys ICC2 Floorplan CTS STA Clock Architecture DFT-Aware PD
ASIC DFT Engineer — 4 to 8 Years (Cisco)
DFT
DFT Scan Insertion ATPG MBIST Boundary Scan JTAG
IO and Mixed Signal Circuit Design Engineer (Broadcom)
Physical Design
IO Design Mixed Signal SPICE Cadence Virtuoso ASIC Circuit Design
FPGA IP Validation Engineer — Entry Level (Altera)
✅ Fresher FriendlyFPGA
FPGA IP Validation Verilog SystemVerilog Intel FPGA Tools
Design Verification Engineer — Entry Level (Eximietas Design)
✅ Fresher FriendlyVerification
SystemVerilog UVM RTL Verification Functional Coverage Assertions
Physical Design Engineer — CTS, STA & Signoff (Seminovaa)
✅ Fresher FriendlyPhysical Design
Physical Design CTS STA EMIR Signoff Place & Route
VLSI CAD Engineer — SoC IP Enablement & Front-End TFM (L&T Semiconductor Technologies)
EDA Tools
VLSI CAD EDA Tools SoC IP Enablement Front-End Design Scripting
VLSI ASIC/SOC Verification Lead/Manager (HCLTech)
Verification
SystemVerilog UVM SoC Verification Formal Verification Team Leadership
Sr. Staff RTL Design Engineer — PCIe (Marvell Technology)
RTL Design
Verilog SystemVerilog PCIe ASIC RTL Design Microarchitecture
ASIC Design Engineer — Smart Edge SoC Security (Axiado Corporation)
SoC Architecture
RTL Design SoC Integration Verilog SystemVerilog Python
ASIC Verification Engineer — GPU & Networking Silicon (NVIDIA)
Verification
SystemVerilog UVM ASIC Verification Functional Coverage Python
Staff Engineer - DFT (Qualcomm)
DFT
DFT Architecture ATPG Scan Test Strategy BIST
Hardware System Engineer – iPhone System Technologies SoC (Apple)
SoC Architecture
SoC Architecture System Design Signal Integrity Power Delivery
SoC Design Verification Engineer (Apple)
✅ Fresher FriendlyVerification
UVM SystemVerilog SoC Verification Testbench Development
GPU SOC Design Engineer (Intel)
AI Silicon
GPU Architecture ASIC Design RTL Verification System Integration
ASIC Verification Engineer - New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM Testbench Development Functional Verification
Formal Verification Engineer - New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog Formal Methods Property Checking RTL Verification
Design Verification Engineer — PCIe Protocol IP (Silicon Patterns)
Verification
PCIe UVM SystemVerilog Protocol Verification IP Verification
Physical Design Engineer — Advanced Node SoC (Altera)
Physical Design
Place & Route Timing Closure Floorplanning CTS STA
Lead Physical Design Engineer — AI NPU (NXP Semiconductors)
Physical Design
Physical Design Flow P&R Timing AI/NPU Architecture ICC2
Senior ASIC RTL Integration and Netlisting Engineer (NVIDIA)
RTL Design
SystemVerilog ASIC Design RTL Coding Logic Synthesis Timing Analysis
Physical Design Engineer — STA, CTS & Signoff (7Rays Semiconductors)
✅ Fresher FriendlyPhysical Design
Static Timing Analysis Cadence Tempus Synopsys PrimeTime CTS Physical Design ECO
DFT Engineer — ASIC IP Verification (AMD)
DFT
ATPG JTAG Scan Insertion UVM VCS Synopsys DFT Compiler Mentor Tessent
Physical Design Engineer Sr Lead — Advanced Node SoC (Qualcomm)
Physical Design
Cadence Innovus STA CTS Floorplanning Power Optimization Deep Submicron ECO
IP Design Verification Engineer — UVM, SoC & Embedded Processors (Texas Instruments)
Verification
SystemVerilog UVM SoC Verification Embedded Processors Functional Coverage Tcl
Principal Engineer — ASIC Pre-Silicon Validation HAPS Prototyping (Micron Technology)
Verification
HAPS Prototyping ZeBu Emulation Pre-Silicon Validation C++ Python DRAM Architecture
SOC/FPGA Design Verification Engineering Lead — Intel Altera (Altera)
FPGA
SystemVerilog UVM FPGA Verification Intel Quartus Protocol Verification SoC Debug
VLSI Engineer — Digital Design & RTL Verification (VLSI FOR ALL)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog VLSI Design Digital Logic EDA Tools RTL Simulation
Verification Engineer — Formal Automation & Property Checking (Iravan Technologies)
✅ Fresher FriendlyVerification
Formal Verification JasperGold SVA Property Specification SystemVerilog Cadence Jasper
Senior ASIC Design Engineer — RTL & Synthesis (NVIDIA)
RTL Design
SystemVerilog Verilog RTL Design Logic Synthesis STA CDC/RDC DFT
Hardware System Engineer — iPhone System Technologies SoC (Apple)
SoC Architecture
C/C++ Python SoC Debug System Architecture Hardware-Software Integration Silicon Validation
Power-Aware SoC Verification Engineer — Entry Level (Chip Smart Technologies)
✅ Fresher FriendlySoC Architecture
SoC Verification UPF Power Domains Low Power Design SystemVerilog UVM
Senior Design Verification Engineer — SoC (MediaTek)
Verification
SystemVerilog UVM Functional Verification SoC Verification Coverage-Driven Verification
DFT Engineer — ASIC Test Architecture (Texas Instruments India)
DFT
DFT Scan Insertion ATPG MBIST JTAG Boundary Scan Silicon Test
Design Verification Engineer — PCIe Protocol IP (Silicon Patterns)
Verification
PCIe SystemVerilog UVM Protocol Verification Constrained Random Functional Coverage
Physical Design Engineer — Full Flow RTL to GDSII (Quest Global)
Physical Design
Physical Design Floorplanning Placement & Route CTS Timing Closure Synopsys ICC2
Physical Design Engineer — FPGA Timing & Floorplan (Altera)
FPGA
FPGA Physical Design Timing Closure CTS Quartus Prime Intel EDA Tools PnR
VLSI Design & Development Engineer — Entry Level (Nxfee Innovation)
✅ Fresher FriendlyRTL Design
VLSI Design Verilog Digital Design FPGA Logic Design Synthesis
Design Verification Engineer — Entry Level (SingleFocus Labs)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verilog Testbench Development Digital Design Simulation
ASIC Design Engineer — Circuits, AI GPU (NVIDIA AI)
AI Silicon
ASIC Design Circuit Design Analog/Mixed-Signal Timing Analysis SPICE Simulation
Staff Design Verification Engineer — SerDes & AMS IPs (Marvell Technology)
Verification
SystemVerilog UVM SerDes Verification Mixed-Signal Simulation AMS Protocol Verification
DFT Engineer — Automotive Grade SoC (NXP Semiconductors)
DFT
DFT ATPG Boundary Scan BIST Automotive ASIC In-Vehicle Networking
Sr Physical Design Engineer — Advanced Node ASIC (Synopsys)
Physical Design
Place & Route STA ECO Floorplanning CTS Synopsys ICC2 Primetime
System-on-Chip Design Engineer — RTL & Integration (Mirafra Technologies)
RTL Design
RTL Design SystemVerilog ASIC Design SoC Integration UVM Formal Verification
Graduate Engineer Trainee — FPGA Design (Yuktha Innovation)
✅ Fresher FriendlyFPGA
FPGA Verilog VHDL RTL Design Xilinx Intel FPGA Digital Design
VLSI Engineer I — Entry Level Design & Verification (Hewlett Packard Enterprise)
✅ Fresher FriendlyVerification
VLSI Design Verification Verilog Digital Logic ASIC Fundamentals EDA Tools
Design Verification Engineer — IP & SoC Level (Interex Semiconductor)
✅ Fresher FriendlyVerification
SystemVerilog UVM Testbench Development SoC Verification ECE/VLSI
SOC Design Engineer — RTL Integration & Chip Frontend (NVIDIA)
SoC Architecture
RTL Integration SystemVerilog SoC Architecture Netlist Padring Design
Wireless SoC Design Engineer — MAC & ASIC Integration (Apple)
SoC Architecture
ASIC Design SoC Integration RTL Design Verilog SystemVerilog Wireless MAC
Senior DFT Design Engineer — Silicon Bring-up (AMD)
DFT
DFT ATPG Scan Insertion JTAG Silicon Bring-up Pattern Debug
Silicon Design Verification Engineer — TPU, Google Cloud (Google)
AI Silicon
SystemVerilog UVM Python RTL Design SoC Verification ASIC DV
DFT Principal Engineer — Advanced SoC Test (onsemi)
DFT
DFT Scan MBIST LBIST JTAG ATPG Tessent Verilog
Systems Architecture Intern — SoC Design (STMicroelectronics)
✅ Fresher FriendlySoC Architecture
Digital Design ARM Cortex SoC Architecture Verilog EDA Tools
Analog Layout Engineer — Entry Level (Modernize Chip Solutions)
✅ Fresher FriendlyPhysical Design
Analog Layout CMOS Cadence Virtuoso DRC LVS Semiconductor Devices
VLSI/Embedded Engineer — Entry Level (ChipSol)
✅ Fresher FriendlyVLSI Design
VLSI Design Verilog Embedded Systems Digital Electronics C/C++
Design Verification Engineer — Silicon and Systems Group (Amazon)
Verification
SystemVerilog UVM Verification Methodology Python AMBA Protocols
Staff ASIC Design Engineer — Networking SoC (Nokia)
RTL Design
Verilog SystemVerilog RTL Design Synthesis Lint CDC Low Power Design
Physical Design Engineer — RTL to GDSII Implementation (TCS)
Physical Design
Physical Design Floorplanning PnR STA Cadence Innovus ICC2 PrimeTime
RTL Engineer — Analog & Mixed Signal SoC (Texas Instruments)
RTL Design
Verilog RTL Design Synthesis Lint CDC Low Power UPF
ASIC Design for Testability Engineer — Silicon (Google)
DFT
DFT Scan Insertion ATPG MBIST JTAG Verilog Python
Senior AI Chip Design Engineer — ASIC Methodologies (NVIDIA)
AI Silicon
Verilog SystemVerilog ASIC Design Python TCL Synthesis STA
VLSI Engineer — Entry Level (VLSI FOR ALL Pvt Limited)
✅ Fresher FriendlyRTL Design
VLSI Design Digital Logic Verilog SystemVerilog ASIC Fundamentals
Staff ASIC Physical Design Engineer (Micron Technology)
Physical Design
ASIC Physical Design P&R CTS STA Power Analysis Advanced Nodes DRC/LVS
DFT Engineer — Silicon Development Group (Tesla)
DFT
DFT Scan Chain BIST ATPG JTAG Synopsys DFT Compiler SoC Tapeout
ASIC RTL Design Engineer — Sr (Qualcomm)
RTL Design
RTL Design SystemVerilog Micro-architecture Synthesis STA IP Cores
SoC Design Verification Engineer (Apple)
Verification
UVM SystemVerilog Computer Architecture Networking Protocol Python
Physical Design Engineer — Advanced Node SoC (MediaTek)
Physical Design
Cadence Innovus Floorplan P&R CTS STA Physical Implementation Advanced Node
Lead Product Engineer — Digital Implementation EDA (Cadence)
EDA Tools
Digital Implementation VLSI Physical Design Timing Analysis EDA Tools Cadence Innovus
Senior Applications Engineer — Verification EDA (Synopsys)
✅ Fresher FriendlyEDA Tools
Digital Verification UVM SystemVerilog EDA Simulation Tools Customer Support
Verification Engineer — AI SoC & GPU Silicon (NVIDIA)
Verification
SystemVerilog UVM Python C++ Simulation Debug Lint/CDC
Power Methodology and Modeling Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyAI Silicon
Power Analysis ML/AI RTL Design Chip Design Flow Python
RTL Design Lead — CPU Team (AMD)
RTL Design
Verilog SystemVerilog RTL Design CPU Architecture Synthesis Perl
Silicon Physical Design Engineer II — Google Cloud (Google)
Physical Design
Innovus ICC2 Place and Route Floorplanning STA Timing Closure
Staff Design Verification Engineer — Power Management (Renesas Electronics)
Verification
SystemVerilog UVM Power Management IC Formal Verification Assertion-Based Verification
Senior Staff Engineer — DFT (Marvell Technology)
DFT
DFT ATPG Scan Insertion BIST TestKompress SynTest
Senior Applications Engineer — EDA Physical Implementation (Synopsys)
EDA Tools
Fusion Compiler Design Compiler ICC2 Place and Route STA Tcl
SoC Physical Design Clocking Engineer (Intel)
SoC Architecture
CTS Clock Tree Synthesis STA ICC2 Place and Route Timing Constraints
FPGA Design Engineer — Defense & Aerospace (HuntingCube)
FPGA
FPGA Verilog VHDL Xilinx Vivado Intel Quartus RTL Design
RTL Design Engineer — Entry Level (IndieSemiC)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design Digital Logic AMBA Protocols
Design Verification Engineer — Entry Level (SocBridge Semiconductors)
✅ Fresher FriendlyVerification
SystemVerilog UVM Digital Logic Verilog Simulation
Engineering Intern — EDA & Silicon Design (Synopsys India)
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EDA Tools Digital Design SystemVerilog Python Linux
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SoC Security Engineer — Platform Architecture (Apple)
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Hardware Security SoC Design Cryptography SystemVerilog Python
Senior FPGA Engineer (Arm)
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FPGA Design Vivado Verilog VHDL High-Speed Protocol Design
SoC Architect (NXP Semiconductors)
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SoC Architecture Microcontroller Design SystemVerilog ASIC Flow
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Deep Learning TensorFlow PyTorch AI Algorithms Python Hardware Optimization
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DFT Architecture Scan Design ATPG Boundary Scan SystemVerilog
VLSI Engineer L3 (Wipro)
RTL Design
VLSI Design RTL Design SystemVerilog Verification Synthesis
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
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SystemVerilog Verilog ASIC Design RTL Design Logic Synthesis DFT Timing Analysis
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ASIC Physical Design Apprenticeship (Synopsys India)
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Physical Design Place & Route ICC2 PrimeTime Timing Closure
Senior DFT Engineer — Advanced Nodes (NXP Semiconductors)
DFT
DFT Scan Architecture MBIST BIST Design Process Variation
SoC Full Chip DV Engineer (Apple)
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SystemVerilog UVM Full-Chip Verification GPU AI Accelerator
IP Logic Design Engineer — PCIe/UCIe (Intel)
RTL Design
RTL Design Verilog Microarchitecture PCIe System Integration
STA Engineer (Qualcomm India)
Physical Design
Static Timing Analysis PrimeTime Timing Closure Advanced Nodes
Sr Physical Design Engineer (Synopsys Noida)
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Physical Design RTL-to-GDS ICC2 Power Performance Area Optimization
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design ASIC Design Flow Synthesis
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DFT
DFT Architecture ATPG Scan Insertion TestGen SoC Design
Staff Engineer — Design Verification (Micron Technology)
Verification
UVM Design Verification Formal Methods Memory IP Testbenches
Senior Design Verification Engineer — AI SoC (Google)
Verification
SystemVerilog UVM Design Verification Python Machine Learning SoC
STA Engineer (Qualcomm)
Physical Design
Static Timing Analysis PrimeTime PathMill Block-level STA Signoff
SoC Full Chip DV Engineer (Apple)
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SystemVerilog Full-Chip Verification UVM Power Analysis Performance
ASIC Design Verification Engineer — New College Grad (NVIDIA)
✅ Fresher FriendlyVerification
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VLSI Engineer L3 — Design Verification (Wipro)
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Staff Engineer — Design Verification (Micron Technology)
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AI Silicon
SystemVerilog UVM GPU Verification Deep Learning Inference
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DFT BIST Scan Architecture Test Compression ATPG
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Physical Design
Place & Route Timing Analysis STA ICC Innovus Power Analysis
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SystemVerilog UVM Formal Verification Python RTL
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
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Verilog ASIC Design Flow RTL Design Synthesis DFT
FPGA Design Engineer — Aerospace & Defense Systems (HCL Tech)
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FPGA Xilinx Vivado VHDL Verilog Timing Closure DO-254
Junior Verification Engineer — Memory Controller IP (Samsung R&D India)
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Graduate Engineer Trainee — RTL Verification (MediaTek India)
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VLSI Design Intern — RF & mmWave Transceiver (Qualcomm India)
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Analog Design RF Circuits Cadence Virtuoso Spectre MATLAB
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AI Silicon Engineer — LPU Compute Architecture (Groq)
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Microarchitecture LLVM Compiler-Hardware Co-design RTL Python
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SoC Architecture Engineer — Neural Engine & AI Accelerator (Apple)
SoC Architecture
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Physical Design Engineer — EMIB Advanced Packaging (Intel)
Physical Design
Floorplanning Placement Routing PrimeTime Calibre Advanced Packaging
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AI for EDA
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FPGA Design Intern — Automotive SoC (STMicroelectronics India)
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EDA Application Engineer — Calibre DRC/LVS Signoff (Siemens EDA)
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Calibre DRC LVS ERC Python Tcl Physical Verification Customer Support
Analog Mixed-Signal Design Engineer — Power Management (Texas Instruments India)
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Analog Circuit Design SPICE Simulation Op-Amps ADC/DAC Cadence Virtuoso Layout
Memory Interface Verification Engineer (Micron Technology)
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RTL Design Engineer — Storage Controller SoC (Marvell)
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DFT Architecture ATPG Scan Insertion MBIST Tessent Boundary Scan
Physical Design Engineer — Advanced Node 3nm/2nm (ARM)
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AI Silicon Architect — TPU/LLM Accelerator Design (Google DeepMind)
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SoC Architecture RISC-V AI Accelerators RTL Design Performance Modeling Python
Senior Physical Design Engineer — Advanced Packaging & Chiplets
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Innovus Floorplanning CTS Power Grid 3DIC HBM Signoff
AI Silicon Architect — LLM Accelerator Design
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EDA Tools Engineer — Static Timing Analysis & Signoff
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PrimeTime STA Tcl Python SPICE Liberty SDC Timing Closure
SoC Integration & Architecture Engineer — Mobile Platform
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SoC Architecture ARM AMBA AXI Cache Coherency Power Management C++
Photonics Integration Engineer — Silicon Photonics
Photonics
Silicon Photonics Optical Modulator PDK Layout Python FDTD Simulation
VLSI Design Intern — Analog Mixed-Signal (Fresher)
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DFT Intern — Scan Insertion & ATPG (Fresher)
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Junior Verification Engineer — Digital SoC (Fresher)
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RTL Design Engineer — GPU Compute Architecture
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FPGA Design Engineer — Data Center Acceleration
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FPGA Verilog HLS OpenCL PCIe DRAM Interfaces Vivado
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Qualcomm
Graduate VLSI Design Engineer — Fresher
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Verification Intern — Chip Verification (Entry Level)
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Senior Verification Engineer — AI SoC
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Physical Design Engineer — 5nm/3nm ASIC
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