Jobs Archive

Browse 3 months of semiconductor & AI roles • Sort by date, experience, or package

Sort by:
Filter:
Coherency Design Verification Engineer — CHI Multicore CPU (7Rays Semiconductors)
Verification
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 Competitive
SystemVerilog UVM CHI Protocol Coherency Verification CPU Verification Coverage
FPGA Developer — Internship + Full-Time (Vicharak)
✅ Fresher FriendlyFPGA
📍 Surat, Gujarat, India
🎓 Internship
💼 Internship
💰 Competitive
FPGA Verilog VHDL Digital Design RISC-V Hardware Description Language
Associate VLSI DFT Engineer — Test Methodologies (UST)
✅ Fresher FriendlyDFT
📍 India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹6–12 LPA
DFT Scan Insertion ATPG BIST Test Coverage Analysis VLSI
DFT Engineer — Next-Gen Chip Architecture (Mettlesemi Systems)
✅ Fresher FriendlyDFT
📍 India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 Competitive
DFT ATPG Scan Chains Boundary Scan Clock Gating Test Architecture
Senior Logic Design Engineer — GPU ASIC RTL (NVIDIA)
RTL Design
📍 Santa Clara, CA, USA
🎓 5–8 Years
💼 Full-time
💰 $150K–200K/yr
SystemVerilog Verilog RTL Design ASIC Synthesis Timing Closure Logic Design
Formal Verification Engineer — ASIC Design (NVIDIA India)
Verification
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 Competitive
Formal Verification JasperGold Questa Formal SystemVerilog ASIC Property Checking
Senior Lead Physical Design Engineer — Snapdragon SoC (Qualcomm)
Physical Design
📍 Noida, India
🎓 6–10 Years
💼 Full-time
💰 ₹32–50 LPA
Physical Design STA CTS Place & Route PrimeTime Snapdragon Advanced Node
DFT Engineer — Snapdragon ASIC Test Architecture (Qualcomm)
DFT
📍 Chennai, India
🎓 3–6 Years
💼 Full-time
💰 ₹18–28 LPA
DFT ATPG Scan Insertion BIST JTAG Test Coverage Boundary Scan
FPGA Prototyping Design Engineer — SoC Integration (Apple)
FPGA
📍 Cupertino, CA, USA
🎓 5–8 Years
💼 Full-time
💰 $160K–220K/yr
FPGA SoC Prototyping Hardware IP Integration Synthesis Place & Route Emulation
RTL Design Engineer — Chiplet Interconnect Technology (AMD)
RTL Design
📍 Ottawa, Canada
🎓 3–6 Years
💼 Full-time
💰 Competitive
RTL Design Verilog SystemVerilog Chiplet Interconnect DFT VLSI Synthesis
DFT Engineer — Snapdragon ASIC Silicon (Qualcomm)
DFT
📍 Chennai, India
🎓 2–5 Years
💼 Full-time
💰 Competitive
DFT ATPG Scan Insertion BIST MBIST Silicon Debug Qualcomm ASIC
Design Verification Engineer — Google Cloud Silicon TPU (Google)
Verification
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 Competitive
SystemVerilog UVM Python Functional Coverage RTL Verification Google Cloud AI
SoC & FPGA Performance Architect — System Modeling (Altera)
FPGA
📍 Bengaluru, India
🎓 5–8 Years
💼 Full-time
💰 Competitive
FPGA Architecture SoC Performance Modeling SystemVerilog C++ Simulation Power Analysis
Principal SoC RTL Design Engineer — High-Speed Interfaces (TylSemi)
RTL Design
📍 Bengaluru, India
🎓 8–12 Years
💼 Full-time
💰 Competitive
RTL Design SystemVerilog SoC Integration PCIe AXI Micro-Architecture Synthesis
Design Verification Engineer — VLSI Semiconductor (Capgemini Engineering)
Verification
📍 Bengaluru, India
🎓 5–8 Years
💼 Full-time
💰 Competitive
SystemVerilog UVM Constraint Random Verification Functional Coverage Semiconductor IP
Silicon Engineer — Platform & Devices, University Graduate 2026 (Google)
✅ Fresher FriendlyAI Silicon
📍 Hyderabad, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 Competitive
SystemVerilog RTL Design Hardware Verification SoC Python Digital Logic
Software Engineering Intern — EDA Tools & Platform (Synopsys)
✅ Fresher FriendlyEDA Tools
📍 Bengaluru, India
🎓 Internship
💼 Internship
💰 Competitive
C++ Python EDA Tools Software Development Data Structures Algorithms
Analog Layout Trainee — Semiconductor Design (Digicomm Semiconductor)
✅ Fresher FriendlyPhysical Design
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 Competitive
Analog Layout Cadence Virtuoso Custom IC Layout LVS DRC Schematic Reading
Senior DFT Engineer — Complex SoC Test Architecture (NXP Semiconductors)
DFT
📍 Bengaluru, India
🎓 5–8 Years
💼 Full-time
💰 Competitive
DFT ATPG Scan Chain JTAG Boundary Scan SoC Test Architecture Mentor TestKompress
Lead Physical Design Engineer — SoC Implementation & Synthesis (Texas Instruments)
Physical Design
📍 Bengaluru, India
🎓 6–10 Years
💼 Full-time
💰 Competitive
Physical Design Synopsys ICC2 Floorplan CTS STA Clock Architecture DFT-Aware PD
ASIC DFT Engineer — 4 to 8 Years (Cisco)
DFT
📍 Hyderabad, India
🎓 5–8 Years
💼 Full-time
💰 ₹28–48 LPA
DFT Scan Insertion ATPG MBIST Boundary Scan JTAG
IO and Mixed Signal Circuit Design Engineer (Broadcom)
Physical Design
📍 Bengaluru, India
🎓 5–9 Years
💼 Full-time
💰 ₹35–60 LPA
IO Design Mixed Signal SPICE Cadence Virtuoso ASIC Circuit Design
FPGA IP Validation Engineer — Entry Level (Altera)
✅ Fresher FriendlyFPGA
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹6–12 LPA
FPGA IP Validation Verilog SystemVerilog Intel FPGA Tools
Design Verification Engineer — Entry Level (Eximietas Design)
✅ Fresher FriendlyVerification
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹5–10 LPA
SystemVerilog UVM RTL Verification Functional Coverage Assertions
Physical Design Engineer — CTS, STA & Signoff (Seminovaa)
✅ Fresher FriendlyPhysical Design
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹5–10 LPA
Physical Design CTS STA EMIR Signoff Place & Route
VLSI CAD Engineer — SoC IP Enablement & Front-End TFM (L&T Semiconductor Technologies)
EDA Tools
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 ₹20–35 LPA
VLSI CAD EDA Tools SoC IP Enablement Front-End Design Scripting
VLSI ASIC/SOC Verification Lead/Manager (HCLTech)
Verification
📍 Bengaluru / Chennai / Hyderabad, India
🎓 8–12 Years
💼 Full-time
💰 ₹40–65 LPA
SystemVerilog UVM SoC Verification Formal Verification Team Leadership
Sr. Staff RTL Design Engineer — PCIe (Marvell Technology)
RTL Design
📍 Bengaluru, India
🎓 8–12 Years
💼 Full-time
💰 ₹45–70 LPA
Verilog SystemVerilog PCIe ASIC RTL Design Microarchitecture
ASIC Design Engineer — Smart Edge SoC Security (Axiado Corporation)
SoC Architecture
📍 Hyderabad, India
🎓 5–8 Years
💼 Full-time
💰 ₹30–50 LPA
RTL Design SoC Integration Verilog SystemVerilog Python
ASIC Verification Engineer — GPU & Networking Silicon (NVIDIA)
Verification
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 ₹28–48 LPA
SystemVerilog UVM ASIC Verification Functional Coverage Python
Staff Engineer - DFT (Qualcomm)
DFT
📍 Bengaluru, Karnataka, India
🎓 8–12 Years
💼 Full-time
💰 ₹30–45 LPA
DFT Architecture ATPG Scan Test Strategy BIST
Hardware System Engineer – iPhone System Technologies SoC (Apple)
SoC Architecture
📍 Cupertino, CA, USA
🎓 5–9 Years
💼 Full-time
💰 $160K–240K/yr
SoC Architecture System Design Signal Integrity Power Delivery
SoC Design Verification Engineer (Apple)
✅ Fresher FriendlyVerification
📍 Cupertino, CA, USA
🎓 0–2 Years (Fresher)
💼 Full-time
💰 $130K–180K/yr
UVM SystemVerilog SoC Verification Testbench Development
GPU SOC Design Engineer (Intel)
AI Silicon
📍 Bengaluru, Karnataka, India
🎓 4–7 Years
💼 Full-time
💰 ₹24–36 LPA
GPU Architecture ASIC Design RTL Verification System Integration
ASIC Verification Engineer - New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
📍 Santa Clara, CA, USA
🎓 0–2 Years (Fresher)
💼 Full-time
💰 $120K–160K/yr
SystemVerilog UVM Testbench Development Functional Verification
Formal Verification Engineer - New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
📍 Santa Clara, CA, USA
🎓 0–2 Years (Fresher)
💼 Full-time
💰 $120K–160K/yr
SystemVerilog Formal Methods Property Checking RTL Verification
Design Verification Engineer — PCIe Protocol IP (Silicon Patterns)
Verification
📍 Bengaluru, Karnataka, India
🎓 3–6 Years
💼 Full-time
💰 ₹18–28 LPA
PCIe UVM SystemVerilog Protocol Verification IP Verification
Physical Design Engineer — Advanced Node SoC (Altera)
Physical Design
📍 Bengaluru, Karnataka, India
🎓 3–6 Years
💼 Full-time
💰 ₹20–30 LPA
Place & Route Timing Closure Floorplanning CTS STA
Lead Physical Design Engineer — AI NPU (NXP Semiconductors)
Physical Design
📍 Hyderabad, Telangana, India
🎓 6–10 Years
💼 Full-time
💰 ₹28–40 LPA
Physical Design Flow P&R Timing AI/NPU Architecture ICC2
Senior ASIC RTL Integration and Netlisting Engineer (NVIDIA)
RTL Design
📍 Santa Clara, CA, USA
🎓 5–9 Years
💼 Full-time
💰 $150K–220K/yr
SystemVerilog ASIC Design RTL Coding Logic Synthesis Timing Analysis
Physical Design Engineer — STA, CTS & Signoff (7Rays Semiconductors)
✅ Fresher FriendlyPhysical Design
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹4–10 LPA
Static Timing Analysis Cadence Tempus Synopsys PrimeTime CTS Physical Design ECO
DFT Engineer — ASIC IP Verification (AMD)
DFT
📍 Hyderabad, India
🎓 3–6 Years
💼 Full-time
💰 ₹20–35 LPA
ATPG JTAG Scan Insertion UVM VCS Synopsys DFT Compiler Mentor Tessent
Physical Design Engineer Sr Lead — Advanced Node SoC (Qualcomm)
Physical Design
📍 Chennai, India
🎓 6–10 Years
💼 Full-time
💰 ₹25–40 LPA
Cadence Innovus STA CTS Floorplanning Power Optimization Deep Submicron ECO
IP Design Verification Engineer — UVM, SoC & Embedded Processors (Texas Instruments)
Verification
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 ₹15–28 LPA
SystemVerilog UVM SoC Verification Embedded Processors Functional Coverage Tcl
Principal Engineer — ASIC Pre-Silicon Validation HAPS Prototyping (Micron Technology)
Verification
📍 Hyderabad, India
🎓 8–12 Years
💼 Full-time
💰 ₹35–55 LPA
HAPS Prototyping ZeBu Emulation Pre-Silicon Validation C++ Python DRAM Architecture
SOC/FPGA Design Verification Engineering Lead — Intel Altera (Altera)
FPGA
📍 Bengaluru, India
🎓 8–12 Years
💼 Full-time
💰 ₹28–45 LPA
SystemVerilog UVM FPGA Verification Intel Quartus Protocol Verification SoC Debug
VLSI Engineer — Digital Design & RTL Verification (VLSI FOR ALL)
✅ Fresher FriendlyRTL Design
📍 Noida, UP, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹3–8 LPA
Verilog SystemVerilog VLSI Design Digital Logic EDA Tools RTL Simulation
Verification Engineer — Formal Automation & Property Checking (Iravan Technologies)
✅ Fresher FriendlyVerification
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹4–8 LPA
Formal Verification JasperGold SVA Property Specification SystemVerilog Cadence Jasper
Senior ASIC Design Engineer — RTL & Synthesis (NVIDIA)
RTL Design
📍 Santa Clara, CA, USA
🎓 5–8 Years
💼 Full-time
💰 $140K–200K/yr
SystemVerilog Verilog RTL Design Logic Synthesis STA CDC/RDC DFT
Hardware System Engineer — iPhone System Technologies SoC (Apple)
SoC Architecture
📍 Cupertino, CA, USA
🎓 5–9 Years
💼 Full-time
💰 $150K–220K/yr
C/C++ Python SoC Debug System Architecture Hardware-Software Integration Silicon Validation
Power-Aware SoC Verification Engineer — Entry Level (Chip Smart Technologies)
✅ Fresher FriendlySoC Architecture
📍 Hyderabad, Telangana, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹4–8 LPA
SoC Verification UPF Power Domains Low Power Design SystemVerilog UVM
Senior Design Verification Engineer — SoC (MediaTek)
Verification
📍 Bengaluru, Karnataka, India
🎓 5–8 Years
💼 Full-time
💰 ₹25–40 LPA
SystemVerilog UVM Functional Verification SoC Verification Coverage-Driven Verification
DFT Engineer — ASIC Test Architecture (Texas Instruments India)
DFT
📍 Bengaluru, Karnataka, India
🎓 3–6 Years
💼 Full-time
💰 ₹15–25 LPA
DFT Scan Insertion ATPG MBIST JTAG Boundary Scan Silicon Test
Design Verification Engineer — PCIe Protocol IP (Silicon Patterns)
Verification
📍 Bengaluru, Karnataka, India
🎓 3–6 Years
💼 Full-time
💰 ₹12–22 LPA
PCIe SystemVerilog UVM Protocol Verification Constrained Random Functional Coverage
Physical Design Engineer — Full Flow RTL to GDSII (Quest Global)
Physical Design
📍 Bengaluru, Karnataka, India
🎓 3–6 Years
💼 Full-time
💰 ₹10–20 LPA
Physical Design Floorplanning Placement & Route CTS Timing Closure Synopsys ICC2
Physical Design Engineer — FPGA Timing & Floorplan (Altera)
FPGA
📍 Bengaluru, Karnataka, India
🎓 5–8 Years
💼 Full-time
💰 ₹18–30 LPA
FPGA Physical Design Timing Closure CTS Quartus Prime Intel EDA Tools PnR
VLSI Design & Development Engineer — Entry Level (Nxfee Innovation)
✅ Fresher FriendlyRTL Design
📍 India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹3–6 LPA
VLSI Design Verilog Digital Design FPGA Logic Design Synthesis
Design Verification Engineer — Entry Level (SingleFocus Labs)
✅ Fresher FriendlyVerification
📍 India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹4–8 LPA
SystemVerilog UVM Verilog Testbench Development Digital Design Simulation
ASIC Design Engineer — Circuits, AI GPU (NVIDIA AI)
AI Silicon
📍 Bengaluru, Karnataka, India
🎓 5–8 Years
💼 Full-time
💰 ₹30–55 LPA
ASIC Design Circuit Design Analog/Mixed-Signal Timing Analysis SPICE Simulation
Staff Design Verification Engineer — SerDes & AMS IPs (Marvell Technology)
Verification
📍 Bengaluru, Karnataka, India
🎓 8–12 Years
💼 Full-time
💰 ₹45–70 LPA
SystemVerilog UVM SerDes Verification Mixed-Signal Simulation AMS Protocol Verification
DFT Engineer — Automotive Grade SoC (NXP Semiconductors)
DFT
📍 Bengaluru, India
🎓 5–9 Years
💼 Full-time
💰 ₹20–35 LPA
DFT ATPG Boundary Scan BIST Automotive ASIC In-Vehicle Networking
Sr Physical Design Engineer — Advanced Node ASIC (Synopsys)
Physical Design
📍 Noida, India
🎓 5–9 Years
💼 Full-time
💰 ₹25–40 LPA
Place & Route STA ECO Floorplanning CTS Synopsys ICC2 Primetime
System-on-Chip Design Engineer — RTL & Integration (Mirafra Technologies)
RTL Design
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 ₹15–25 LPA
RTL Design SystemVerilog ASIC Design SoC Integration UVM Formal Verification
Graduate Engineer Trainee — FPGA Design (Yuktha Innovation)
✅ Fresher FriendlyFPGA
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹3–5 LPA
FPGA Verilog VHDL RTL Design Xilinx Intel FPGA Digital Design
VLSI Engineer I — Entry Level Design & Verification (Hewlett Packard Enterprise)
✅ Fresher FriendlyVerification
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹10–16 LPA
VLSI Design Verification Verilog Digital Logic ASIC Fundamentals EDA Tools
Design Verification Engineer — IP & SoC Level (Interex Semiconductor)
✅ Fresher FriendlyVerification
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹6–12 LPA
SystemVerilog UVM Testbench Development SoC Verification ECE/VLSI
SOC Design Engineer — RTL Integration & Chip Frontend (NVIDIA)
SoC Architecture
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 Competitive
RTL Integration SystemVerilog SoC Architecture Netlist Padring Design
Wireless SoC Design Engineer — MAC & ASIC Integration (Apple)
SoC Architecture
📍 Santa Clara, CA, USA
🎓 5–8 Years
💼 Full-time
💰 $160K–220K/yr
ASIC Design SoC Integration RTL Design Verilog SystemVerilog Wireless MAC
Senior DFT Design Engineer — Silicon Bring-up (AMD)
DFT
📍 Bengaluru, India
🎓 5–9 Years
💼 Full-time
💰 Competitive
DFT ATPG Scan Insertion JTAG Silicon Bring-up Pattern Debug
Silicon Design Verification Engineer — TPU, Google Cloud (Google)
AI Silicon
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 Competitive
SystemVerilog UVM Python RTL Design SoC Verification ASIC DV
DFT Principal Engineer — Advanced SoC Test (onsemi)
DFT
📍 Bengaluru, India
🎓 8–12 Years
💼 Full-time
💰 Competitive
DFT Scan MBIST LBIST JTAG ATPG Tessent Verilog
Systems Architecture Intern — SoC Design (STMicroelectronics)
✅ Fresher FriendlySoC Architecture
📍 Noida, India
🎓 Internship
💼 Internship
💰 Stipend
Digital Design ARM Cortex SoC Architecture Verilog EDA Tools
Analog Layout Engineer — Entry Level (Modernize Chip Solutions)
✅ Fresher FriendlyPhysical Design
📍 Hyderabad, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹3–6 LPA
Analog Layout CMOS Cadence Virtuoso DRC LVS Semiconductor Devices
VLSI/Embedded Engineer — Entry Level (ChipSol)
✅ Fresher FriendlyVLSI Design
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹4–8 LPA
VLSI Design Verilog Embedded Systems Digital Electronics C/C++
Design Verification Engineer — Silicon and Systems Group (Amazon)
Verification
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 Competitive
SystemVerilog UVM Verification Methodology Python AMBA Protocols
Staff ASIC Design Engineer — Networking SoC (Nokia)
RTL Design
📍 Bengaluru, India
🎓 6–10 Years
💼 Full-time
💰 Competitive
Verilog SystemVerilog RTL Design Synthesis Lint CDC Low Power Design
Physical Design Engineer — RTL to GDSII Implementation (TCS)
Physical Design
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 ₹12–22 LPA
Physical Design Floorplanning PnR STA Cadence Innovus ICC2 PrimeTime
RTL Engineer — Analog & Mixed Signal SoC (Texas Instruments)
RTL Design
📍 Bengaluru, India
🎓 5–9 Years
💼 Full-time
💰 Competitive
Verilog RTL Design Synthesis Lint CDC Low Power UPF
ASIC Design for Testability Engineer — Silicon (Google)
DFT
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 Competitive
DFT Scan Insertion ATPG MBIST JTAG Verilog Python
Senior AI Chip Design Engineer — ASIC Methodologies (NVIDIA)
AI Silicon
📍 Santa Clara, CA, USA
🎓 5–9 Years
💼 Full-time
💰 $160K–220K/yr
Verilog SystemVerilog ASIC Design Python TCL Synthesis STA
VLSI Engineer — Entry Level (VLSI FOR ALL Pvt Limited)
✅ Fresher FriendlyRTL Design
📍 Noida, Uttar Pradesh, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹3–6 LPA
VLSI Design Digital Logic Verilog SystemVerilog ASIC Fundamentals
Staff ASIC Physical Design Engineer (Micron Technology)
Physical Design
📍 Bengaluru, Karnataka, India
🎓 6–10 Years
💼 Full-time
💰 ₹28–40 LPA
ASIC Physical Design P&R CTS STA Power Analysis Advanced Nodes DRC/LVS
DFT Engineer — Silicon Development Group (Tesla)
DFT
📍 Bengaluru, Karnataka, India
🎓 3–6 Years
💼 Full-time
💰 ₹18–28 LPA
DFT Scan Chain BIST ATPG JTAG Synopsys DFT Compiler SoC Tapeout
ASIC RTL Design Engineer — Sr (Qualcomm)
RTL Design
📍 Bengaluru, Karnataka, India
🎓 5–8 Years
💼 Full-time
💰 ₹25–40 LPA
RTL Design SystemVerilog Micro-architecture Synthesis STA IP Cores
SoC Design Verification Engineer (Apple)
Verification
📍 Cupertino, CA, USA
🎓 3–6 Years
💼 Full-time
💰 $140K–190K/yr
UVM SystemVerilog Computer Architecture Networking Protocol Python
Physical Design Engineer — Advanced Node SoC (MediaTek)
Physical Design
📍 Bengaluru, Karnataka, India
🎓 5–8 Years
💼 Full-time
💰 ₹20–32 LPA
Cadence Innovus Floorplan P&R CTS STA Physical Implementation Advanced Node
Lead Product Engineer — Digital Implementation EDA (Cadence)
EDA Tools
📍 Noida, Uttar Pradesh, India
🎓 4–7 Years
💼 Full-time
💰 ₹15–22 LPA
Digital Implementation VLSI Physical Design Timing Analysis EDA Tools Cadence Innovus
Senior Applications Engineer — Verification EDA (Synopsys)
✅ Fresher FriendlyEDA Tools
📍 Bengaluru, Karnataka, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹8–14 LPA
Digital Verification UVM SystemVerilog EDA Simulation Tools Customer Support
Verification Engineer — AI SoC & GPU Silicon (NVIDIA)
Verification
📍 Bengaluru, India / Global
🎓 3–6 Years
💼 Full-time
💰 $120K–160K/yr
SystemVerilog UVM Python C++ Simulation Debug Lint/CDC
Power Methodology and Modeling Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyAI Silicon
📍 Santa Clara, CA, USA
🎓 0–2 Years (Fresher)
💼 Full-time
💰 $85K–115K/yr
Power Analysis ML/AI RTL Design Chip Design Flow Python
RTL Design Lead — CPU Team (AMD)
RTL Design
📍 Bengaluru, Karnataka, India
🎓 8–12 Years
💼 Full-time
💰 ₹30–50 LPA
Verilog SystemVerilog RTL Design CPU Architecture Synthesis Perl
Silicon Physical Design Engineer II — Google Cloud (Google)
Physical Design
📍 Bengaluru, Karnataka, India
🎓 3–6 Years
💼 Full-time
💰 ₹30–50 LPA
Innovus ICC2 Place and Route Floorplanning STA Timing Closure
Staff Design Verification Engineer — Power Management (Renesas Electronics)
Verification
📍 Bengaluru, Karnataka, India
🎓 8–12 Years
💼 Full-time
💰 ₹25–40 LPA
SystemVerilog UVM Power Management IC Formal Verification Assertion-Based Verification
Senior Staff Engineer — DFT (Marvell Technology)
DFT
📍 Bengaluru, Karnataka, India
🎓 8–12 Years
💼 Full-time
💰 ₹35–55 LPA
DFT ATPG Scan Insertion BIST TestKompress SynTest
Senior Applications Engineer — EDA Physical Implementation (Synopsys)
EDA Tools
📍 Bengaluru, Karnataka, India
🎓 5–8 Years
💼 Full-time
💰 ₹20–35 LPA
Fusion Compiler Design Compiler ICC2 Place and Route STA Tcl
SoC Physical Design Clocking Engineer (Intel)
SoC Architecture
📍 Bengaluru, Karnataka, India
🎓 5–8 Years
💼 Full-time
💰 ₹18–30 LPA
CTS Clock Tree Synthesis STA ICC2 Place and Route Timing Constraints
FPGA Design Engineer — Defense & Aerospace (HuntingCube)
FPGA
📍 Gurugram, Haryana, India
🎓 3–6 Years
💼 Full-time
💰 ₹12–20 LPA
FPGA Verilog VHDL Xilinx Vivado Intel Quartus RTL Design
RTL Design Engineer — Entry Level (IndieSemiC)
✅ Fresher FriendlyRTL Design
📍 Ahmedabad, Gujarat, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹4–8 LPA
Verilog SystemVerilog RTL Design Digital Logic AMBA Protocols
Design Verification Engineer — Entry Level (SocBridge Semiconductors)
✅ Fresher FriendlyVerification
📍 India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹4–8 LPA
SystemVerilog UVM Digital Logic Verilog Simulation
Engineering Intern — EDA & Silicon Design (Synopsys India)
✅ Fresher FriendlyEDA Tools
📍 Bengaluru / Noida / Hyderabad, India
🎓 Internship
💼 Internship
💰 Competitive Stipend
EDA Tools Digital Design SystemVerilog Python Linux
Debug Tools SoC Design Engineer (Apple)
SoC Architecture
📍 Cupertino, CA, USA
🎓 3–6 Years
💼 Full-time
💰 $160K–220K/yr
SoC Architecture SystemVerilog JTAG Debug Protocols C++
SoC Security Engineer — Platform Architecture (Apple)
SoC Architecture
📍 Cupertino, CA, USA
🎓 5–9 Years
💼 Full-time
💰 $180K–240K/yr
Hardware Security SoC Design Cryptography SystemVerilog Python
Senior FPGA Engineer (Arm)
FPGA
📍 Bengaluru, Karnataka, India
🎓 6–10 Years
💼 Full-time
💰 ₹30–45 LPA
FPGA Design Vivado Verilog VHDL High-Speed Protocol Design
SoC Architect (NXP Semiconductors)
SoC Architecture
📍 Pune, Maharashtra, India
🎓 8–12 Years
💼 Full-time
💰 ₹35–50 LPA
SoC Architecture Microcontroller Design SystemVerilog ASIC Flow
AI ML Engineer (Qualcomm)
AI Silicon
📍 Hyderabad, Telangana, India
🎓 2–4 Years
💼 Full-time
💰 ₹16–25 LPA
Deep Learning TensorFlow PyTorch AI Algorithms Python Hardware Optimization
DFT Engineer (Texas Instruments India)
DFT
📍 Bengaluru, Karnataka, India
🎓 3–6 Years
💼 Full-time
💰 ₹20–30 LPA
DFT Architecture Scan Design ATPG Boundary Scan SystemVerilog
VLSI Engineer L3 (Wipro)
RTL Design
📍 Bengaluru, Karnataka, India
🎓 4–7 Years
💼 Full-time
💰 ₹18–28 LPA
VLSI Design RTL Design SystemVerilog Verification Synthesis
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyASIC Design
📍 Santa Clara, CA, USA
🎓 0–2 Years (Fresher)
💼 Full-time
💰 $100K–140K/yr
SystemVerilog Verilog ASIC Design RTL Design Logic Synthesis DFT Timing Analysis
ASIC Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
📍 Santa Clara, CA, USA
🎓 0–2 Years (Fresher)
💼 Full-time
💰 $105K–145K/yr
SystemVerilog UVM Verification Python Formal Methods
ASIC RTL Integration and Netlisting Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
📍 Santa Clara, CA, USA
🎓 0–2 Years (Fresher)
💼 Full-time
💰 $110K–150K/yr
Verilog RTL Design Logic Synthesis Netlist Integration Perl
ASIC Physical Design Apprenticeship (Synopsys India)
✅ Fresher FriendlyPhysical Design
📍 Noida, India
🎓 Internship
💼 Full-time
💰 ₹6–12 LPA
Physical Design Place & Route ICC2 PrimeTime Timing Closure
Senior DFT Engineer — Advanced Nodes (NXP Semiconductors)
DFT
📍 Bengaluru, India
🎓 6–10 Years
💼 Full-time
💰 ₹22–34 LPA
DFT Scan Architecture MBIST BIST Design Process Variation
SoC Full Chip DV Engineer (Apple)
Verification
📍 USA
🎓 5–9 Years
💼 Full-time
💰 $150K–220K/yr
SystemVerilog UVM Full-Chip Verification GPU AI Accelerator
IP Logic Design Engineer — PCIe/UCIe (Intel)
RTL Design
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 ₹16–24 LPA
RTL Design Verilog Microarchitecture PCIe System Integration
STA Engineer (Qualcomm India)
Physical Design
📍 Bengaluru, India
🎓 5–9 Years
💼 Full-time
💰 ₹18–28 LPA
Static Timing Analysis PrimeTime Timing Closure Advanced Nodes
Sr Physical Design Engineer (Synopsys Noida)
Physical Design
📍 Noida, India
🎓 6–10 Years
💼 Full-time
💰 ₹22–34 LPA
Physical Design RTL-to-GDS ICC2 Power Performance Area Optimization
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
📍 Santa Clara, CA, USA
🎓 0–2 Years (Fresher)
💼 Full-time
💰 $120K–160K/yr
Verilog SystemVerilog RTL Design ASIC Design Flow Synthesis
Senior DFT Engineer — Memory/GPU SoC (AMD)
DFT
📍 Bengaluru, India
🎓 5–8 Years
💼 Full-time
💰 ₹20–32 LPA
DFT Architecture ATPG Scan Insertion TestGen SoC Design
Staff Engineer — Design Verification (Micron Technology)
Verification
📍 Hyderabad, India
🎓 8–12 Years
💼 Full-time
💰 ₹28–42 LPA
UVM Design Verification Formal Methods Memory IP Testbenches
Senior Design Verification Engineer — AI SoC (Google)
Verification
📍 Bengaluru, India
🎓 5–8 Years
💼 Full-time
💰 ₹18–28 LPA
SystemVerilog UVM Design Verification Python Machine Learning SoC
STA Engineer (Qualcomm)
Physical Design
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 ₹18–30 LPA
Static Timing Analysis PrimeTime PathMill Block-level STA Signoff
SoC Full Chip DV Engineer (Apple)
Verification
📍 Austin, TX, USA
🎓 6–10 Years
💼 Full-time
💰 $150K–220K/yr
SystemVerilog Full-Chip Verification UVM Power Analysis Performance
ASIC Design Verification Engineer — New College Grad (NVIDIA)
✅ Fresher FriendlyVerification
📍 Santa Clara, CA, USA
🎓 0–2 Years (Fresher)
💼 Full-time
💰 $110K–150K/yr
SystemVerilog Verilog Testbench Development Verification Methodology
VLSI Engineer L3 — Design Verification (Wipro)
✅ Fresher FriendlyVerification
📍 Bengaluru, India
🎓 Internship
💼 Full-time
💰 ₹10–16 LPA
SystemVerilog UVM Python Design Verification Testbench Development
Staff Engineer — Design Verification (Micron Technology)
Verification
📍 Hyderabad, India
🎓 6–10 Years
💼 Full-time
💰 ₹30–50 LPA
SystemVerilog Memory Interface Verification UVM Formal Methods
Senior Design Verification Engineer — GPU SoC (Mythic)
AI Silicon
📍 Bengaluru, India
🎓 5–7 Years
💼 Full-time
💰 ₹28–42 LPA
SystemVerilog UVM GPU Verification Deep Learning Inference
Senior DFT Engineer — GPU SoC (AMD)
DFT
📍 Bengaluru, India
🎓 5–9 Years
💼 Full-time
💰 ₹30–48 LPA
DFT BIST Scan Architecture Test Compression ATPG
Sr Physical Design Engineer (Synopsys)
Physical Design
📍 Noida, India
🎓 5–8 Years
💼 Full-time
💰 ₹28–42 LPA
Place & Route Timing Analysis STA ICC Innovus Power Analysis
Senior Design Verification Engineer — Silicon Cloud (Google)
Verification
📍 Bengaluru, India
🎓 5–8 Years
💼 Full-time
💰 ₹25–45 LPA
SystemVerilog UVM Formal Verification Python RTL
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
📍 Santa Clara, CA, USA
🎓 0–2 Years (Fresher)
💼 Full-time
💰 $120K–160K/yr
Verilog ASIC Design Flow RTL Design Synthesis DFT
FPGA Design Engineer — Aerospace & Defense Systems (HCL Tech)
FPGA
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 ₹18–28 LPA
FPGA Xilinx Vivado VHDL Verilog Timing Closure DO-254
Junior Verification Engineer — Memory Controller IP (Samsung R&D India)
✅ Fresher FriendlyVerification
📍 Noida, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹10–16 LPA
SystemVerilog UVM LPDDR5 AXI Protocol Assertion-Based Verification
Graduate Engineer Trainee — RTL Verification (MediaTek India)
✅ Fresher FriendlyVerification
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹12–18 LPA
SystemVerilog UVM basics Digital Design Verilog Python
VLSI Design Intern — RF & mmWave Transceiver (Qualcomm India)
✅ Fresher FriendlyAnalog/RF Design
📍 Hyderabad, India
🎓 Internship
💼 Internship
💰 ₹60K–80K/month stipend
Analog Design RF Circuits Cadence Virtuoso Spectre MATLAB
EDA Application Engineer — Virtuoso Custom Layout & AMS (Cadence)
EDA Tools
📍 San Jose, CA, USA
🎓 3–6 Years
💼 Full-time
💰 $120K–175K/yr
Cadence Virtuoso Spectre AMS Simulation SKILL scripting DRC/LVS
AI Silicon Engineer — LPU Compute Architecture (Groq)
AI Silicon
📍 Mountain View, CA, USA
🎓 5–10 Years
💼 Full-time
💰 $160K–230K/yr
Microarchitecture LLVM Compiler-Hardware Co-design RTL Python
Senior DFT Engineer — GPU SoC Scan & BIST (AMD)
DFT
📍 Austin, TX, USA
🎓 4–8 Years
💼 Full-time
💰 $130K–185K/yr
DFT Scan Insertion ATPG BIST Tessent Mentor FASTSCAN
SoC Architecture Engineer — Neural Engine & AI Accelerator (Apple)
SoC Architecture
📍 Cupertino, CA, USA
🎓 6–10 Years
💼 Full-time
💰 $170K–240K/yr
SoC Architecture Microarchitecture AI/ML Accelerators Performance Modeling C++
Physical Design Engineer — EMIB Advanced Packaging (Intel)
Physical Design
📍 Hillsboro, OR, USA
🎓 4–7 Years
💼 Full-time
💰 $130K–190K/yr
Floorplanning Placement Routing PrimeTime Calibre Advanced Packaging
Senior RTL Design Engineer — GPU Architecture (NVIDIA)
RTL Design
📍 Santa Clara, CA, USA
🎓 5–9 Years
💼 Full-time
💰 $150K–220K/yr
SystemVerilog RTL Design Microarchitecture Python RISC-V
ASIC Design Engineer (Circuits) — NVIDIA
AI Silicon
📍 Bengaluru, India
🎓 4-8 years
💼 Full-time
💰 30-50 LPA
Staff Engineer — RTL Design — NXP Semiconductors
RTL Design
📍 Noida, India
🎓 6-10 years
💼 Full-time
💰 28-42 LPA
Sr Staff Formal Verification R&D Engineer — Synopsys
AI for EDA
📍 Bengaluru, India
🎓 8+ years
💼 Full-time
💰 40-65 LPA
Principal ASIC Physical Design Engineer — Synopsys
Physical Design
📍 Bengaluru, India
🎓 10+ years
💼 Full-time
💰 45-70 LPA
RTL Design Engineer — Sr. Lead — Qualcomm
RTL Design
📍 Hyderabad, India
🎓 8+ years
💼 Full-time
💰 35-55 LPA
Senior Design Verification Engineer — NXP Semiconductors
Verification
📍 Noida, India
🎓 5-10 years
💼 Full-time
💰 25-40 LPA
Design Verification Engineer — PravegaSemi PVT LTD
✅ Fresher FriendlyVerification
📍 Bengaluru, India
🎓 0-2 years
💼 Full-time
💰 7-12 LPA
RTL Design Engineer — BOLTCHIP
RTL Design
📍 Hyderabad, India
🎓 2-5 years
💼 Full-time
💰 10-18 LPA
DFT Engineer — BigEndian Semiconductors
✅ Fresher FriendlyDFT/Test
📍 Bengaluru, India
🎓 0-2 years
💼 Full-time
💰 6-12 LPA
Digital Engineer — Texas Instruments India
✅ Fresher FriendlyRTL Design
📍 Bengaluru, India
🎓 0-2 years
💼 Full-time
💰 8-14 LPA
Junior Verification Engineer — Mixed-Signal IP (Analog Devices India)
✅ Fresher FriendlyVerification
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹6–10 LPA
SystemVerilog UVM Basics Testbench Development Analog IP Verification Python
Graduate Engineer Trainee — VLSI RTL Design (Wipro VLSI)
✅ Fresher FriendlyRTL Design
📍 Bengaluru, India
🎓 0–1 Year (Fresher)
💼 Full-time
💰 ₹4.5–6.5 LPA
Verilog SystemVerilog Digital Design Logic Synthesis Questa/ModelSim
FPGA Design Intern — Automotive SoC (STMicroelectronics India)
✅ Fresher FriendlyFPGA
📍 Noida, India
🎓 Internship
💼 Internship
💰 ₹25–35K/month
FPGA Verilog/VHDL Xilinx/Intel FPGA Tools Digital Design Basics Simulation
EDA Application Engineer — Calibre DRC/LVS Signoff (Siemens EDA)
EDA Tools
📍 Pune, India
🎓 4–7 Years
💼 Full-time
💰 ₹22–38 LPA
Calibre DRC LVS ERC Python Tcl Physical Verification Customer Support
Analog Mixed-Signal Design Engineer — Power Management (Texas Instruments India)
Analog/Mixed-Signal
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 ₹20–35 LPA
Analog Circuit Design SPICE Simulation Op-Amps ADC/DAC Cadence Virtuoso Layout
Memory Interface Verification Engineer (Micron Technology)
Verification
📍 Boise, ID, USA
🎓 4–7 Years
💼 Full-time
💰 $120K–165K/yr
SystemVerilog UVM DDR5 LPDDR5 Memory Protocols Python Assertions
RTL Design Engineer — Storage Controller SoC (Marvell)
RTL Design
📍 Santa Clara, CA, USA
🎓 3–6 Years
💼 Full-time
💰 $125K–170K/yr
SystemVerilog RTL Design Microarchitecture NVMe PCIe CDC Analysis
Senior DFT Engineer — Networking SoC (Broadcom)
DFT
📍 San Jose, CA, USA
🎓 5–8 Years
💼 Full-time
💰 $145K–195K/yr
DFT Architecture ATPG Scan Insertion MBIST Tessent Boundary Scan
Physical Design Engineer — Advanced Node 3nm/2nm (ARM)
Physical Design
📍 Austin, TX, USA
🎓 3–6 Years
💼 Full-time
💰 $130K–175K/yr
Floorplanning Place & Route STA Clock Tree Synthesis Innovus PrimeTime
AI Silicon Architect — TPU/LLM Accelerator Design (Google DeepMind)
AI Silicon
📍 Mountain View, CA, USA
🎓 6–10 Years
💼 Full-time
💰 $180K–260K/yr
SoC Architecture RISC-V AI Accelerators RTL Design Performance Modeling Python
Senior Physical Design Engineer — Advanced Packaging & Chiplets
Physical Design
📍 San Jose, CA, USA
🎓 6–10 Years
💼 Full-time
💰 $150K–210K/yr
Innovus Floorplanning CTS Power Grid 3DIC HBM Signoff
AI Silicon Architect — LLM Accelerator Design
AI Silicon
📍 Mountain View, CA, USA
🎓 7–12 Years
💼 Full-time
💰 $170K–240K/yr
SoC Architecture LLM Inference NoC Design Memory Subsystems RISC-V C++
EDA Tools Engineer — Static Timing Analysis & Signoff
EDA Tools
📍 Mountain View, CA, USA
🎓 5–9 Years
💼 Full-time
💰 $135K–195K/yr
PrimeTime STA Tcl Python SPICE Liberty SDC Timing Closure
SoC Integration & Architecture Engineer — Mobile Platform
SoC Architecture
📍 San Diego, CA, USA
🎓 5–10 Years
💼 Full-time
💰 $145K–205K/yr
SoC Architecture ARM AMBA AXI Cache Coherency Power Management C++
Photonics Integration Engineer — Silicon Photonics
Photonics
📍 Santa Clara, CA, USA
🎓 4–8 Years
💼 Full-time
💰 $130K–185K/yr
Silicon Photonics Optical Modulator PDK Layout Python FDTD Simulation
VLSI Design Intern — Analog Mixed-Signal (Fresher)
✅ Fresher FriendlyRTL Design
📍 Bengaluru, India
🎓 Internship
💼 Internship
💰 ₹50K–70K/month stipend
CMOS Design Analog Layout Cadence Virtuoso SPICE Verilog-AMS
DFT Intern — Scan Insertion & ATPG (Fresher)
✅ Fresher FriendlyDFT
📍 Hyderabad, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹12–18 LPA
DFT ATPG Tessent JTAG Boundary Scan Verilog Python
Junior Verification Engineer — Digital SoC (Fresher)
✅ Fresher FriendlyVerification
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹10–16 LPA
SystemVerilog UVM Functional Coverage Assertions Python Git
RTL Design Engineer — GPU Compute Architecture
RTL Design
📍 Santa Clara, CA, USA
🎓 4–7 Years
💼 Full-time
💰 $130K–190K/yr
SystemVerilog RTL Design UVM Python Synthesis Timing Closure
FPGA Design Engineer — Data Center Acceleration
FPGA
📍 Hillsboro, OR, USA
🎓 3–6 Years
💼 Full-time
💰 $125K–175K/yr
FPGA Verilog HLS OpenCL PCIe DRAM Interfaces Vivado
Groq
DFT Engineer — AI Accelerator Chips
DFT
📍 Mountain View, CA / Remote
🎓 3–6 years
💼 Full-time
💰 $160k–$210k + equity
ATPG MBIST Scan Compression Tessent Design Compiler JTAG
Qualcomm
Graduate VLSI Design Engineer — Fresher
✅ Fresher FriendlyRTL Design
📍 Bangalore, India / Hybrid
🎓 0–1 year (Freshers welcome)
💼 Full-time
💰 INR 18–22 LPA
Verilog SystemVerilog Digital Design CMOS fundamentals VLSI
Texas Instruments
Verification Intern — Chip Verification (Entry Level)
✅ Fresher FriendlyVerification
📍 Dallas, TX / Bangalore, India
🎓 Entry Level — 0–2 years or final year students
💼 Internship / Full-time
💰 $35–45/hr (Intern) | INR 10–15 LPA (FTE)
SystemVerilog UVM basics Python Scripting RISC-V architecture
NVIDIA
Senior Verification Engineer — AI SoC
AI Silicon
📍 Santa Clara, CA / Hybrid
🎓 5–8 years
💼 Full-time
💰 $180k–$240k + equity
SystemVerilog UVM Formal Verification Assertion-Based Verification Python
Apple Silicon
Physical Design Engineer — 5nm/3nm ASIC
Physical Design
📍 Cupertino, CA
🎓 4–7 years
💼 Full-time
💰 $175k–$230k + equity
Innovus Tempus Calibre TCL scripting STA Low-Power Design

Stay Ahead in VLSI + AI

Daily jobs, resources & insights — curated for semiconductor engineers.

🎉

You're In!

Welcome to the VLSIChaps community. Check your inbox for a welcome email!

📲 Join 20K+ Engineers