Jobs Archive
Browse 3 months of semiconductor & AI roles • Sort by date, experience, or package
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Coherency Design Verification Engineer — CHI Multicore CPU (7Rays Semiconductors)
Verification
SystemVerilog UVM CHI Protocol Coherency Verification CPU Verification Coverage
FPGA Developer — Internship + Full-Time (Vicharak)
✅ Fresher FriendlyFPGA
FPGA Verilog VHDL Digital Design RISC-V Hardware Description Language
Associate VLSI DFT Engineer — Test Methodologies (UST)
✅ Fresher FriendlyDFT
DFT Scan Insertion ATPG BIST Test Coverage Analysis VLSI
DFT Engineer — Next-Gen Chip Architecture (Mettlesemi Systems)
✅ Fresher FriendlyDFT
DFT ATPG Scan Chains Boundary Scan Clock Gating Test Architecture
Senior Logic Design Engineer — GPU ASIC RTL (NVIDIA)
RTL Design
SystemVerilog Verilog RTL Design ASIC Synthesis Timing Closure Logic Design
Formal Verification Engineer — ASIC Design (NVIDIA India)
Verification
Formal Verification JasperGold Questa Formal SystemVerilog ASIC Property Checking
Senior Lead Physical Design Engineer — Snapdragon SoC (Qualcomm)
Physical Design
Physical Design STA CTS Place & Route PrimeTime Snapdragon Advanced Node
DFT Engineer — Snapdragon ASIC Test Architecture (Qualcomm)
DFT
DFT ATPG Scan Insertion BIST JTAG Test Coverage Boundary Scan
FPGA Prototyping Design Engineer — SoC Integration (Apple)
FPGA
FPGA SoC Prototyping Hardware IP Integration Synthesis Place & Route Emulation
RTL Design Engineer — Chiplet Interconnect Technology (AMD)
RTL Design
RTL Design Verilog SystemVerilog Chiplet Interconnect DFT VLSI Synthesis
DFT Engineer — Snapdragon ASIC Silicon (Qualcomm)
DFT
DFT ATPG Scan Insertion BIST MBIST Silicon Debug Qualcomm ASIC
Design Verification Engineer — Google Cloud Silicon TPU (Google)
Verification
SystemVerilog UVM Python Functional Coverage RTL Verification Google Cloud AI
SoC & FPGA Performance Architect — System Modeling (Altera)
FPGA
FPGA Architecture SoC Performance Modeling SystemVerilog C++ Simulation Power Analysis
Principal SoC RTL Design Engineer — High-Speed Interfaces (TylSemi)
RTL Design
RTL Design SystemVerilog SoC Integration PCIe AXI Micro-Architecture Synthesis
Design Verification Engineer — VLSI Semiconductor (Capgemini Engineering)
Verification
SystemVerilog UVM Constraint Random Verification Functional Coverage Semiconductor IP
Silicon Engineer — Platform & Devices, University Graduate 2026 (Google)
✅ Fresher FriendlyAI Silicon
SystemVerilog RTL Design Hardware Verification SoC Python Digital Logic
Software Engineering Intern — EDA Tools & Platform (Synopsys)
✅ Fresher FriendlyEDA Tools
C++ Python EDA Tools Software Development Data Structures Algorithms
Analog Layout Trainee — Semiconductor Design (Digicomm Semiconductor)
✅ Fresher FriendlyPhysical Design
Analog Layout Cadence Virtuoso Custom IC Layout LVS DRC Schematic Reading
Senior DFT Engineer — Complex SoC Test Architecture (NXP Semiconductors)
DFT
DFT ATPG Scan Chain JTAG Boundary Scan SoC Test Architecture Mentor TestKompress
Lead Physical Design Engineer — SoC Implementation & Synthesis (Texas Instruments)
Physical Design
Physical Design Synopsys ICC2 Floorplan CTS STA Clock Architecture DFT-Aware PD
ASIC DFT Engineer — 4 to 8 Years (Cisco)
DFT
DFT Scan Insertion ATPG MBIST Boundary Scan JTAG
IO and Mixed Signal Circuit Design Engineer (Broadcom)
Physical Design
IO Design Mixed Signal SPICE Cadence Virtuoso ASIC Circuit Design
FPGA IP Validation Engineer — Entry Level (Altera)
✅ Fresher FriendlyFPGA
FPGA IP Validation Verilog SystemVerilog Intel FPGA Tools
Design Verification Engineer — Entry Level (Eximietas Design)
✅ Fresher FriendlyVerification
SystemVerilog UVM RTL Verification Functional Coverage Assertions
Physical Design Engineer — CTS, STA & Signoff (Seminovaa)
✅ Fresher FriendlyPhysical Design
Physical Design CTS STA EMIR Signoff Place & Route
VLSI CAD Engineer — SoC IP Enablement & Front-End TFM (L&T Semiconductor Technologies)
EDA Tools
VLSI CAD EDA Tools SoC IP Enablement Front-End Design Scripting
VLSI ASIC/SOC Verification Lead/Manager (HCLTech)
Verification
SystemVerilog UVM SoC Verification Formal Verification Team Leadership
Sr. Staff RTL Design Engineer — PCIe (Marvell Technology)
RTL Design
Verilog SystemVerilog PCIe ASIC RTL Design Microarchitecture
ASIC Design Engineer — Smart Edge SoC Security (Axiado Corporation)
SoC Architecture
RTL Design SoC Integration Verilog SystemVerilog Python
ASIC Verification Engineer — GPU & Networking Silicon (NVIDIA)
Verification
SystemVerilog UVM ASIC Verification Functional Coverage Python
Staff Engineer - DFT (Qualcomm)
DFT
DFT Architecture ATPG Scan Test Strategy BIST
Hardware System Engineer – iPhone System Technologies SoC (Apple)
SoC Architecture
SoC Architecture System Design Signal Integrity Power Delivery
SoC Design Verification Engineer (Apple)
✅ Fresher FriendlyVerification
UVM SystemVerilog SoC Verification Testbench Development
GPU SOC Design Engineer (Intel)
AI Silicon
GPU Architecture ASIC Design RTL Verification System Integration
ASIC Verification Engineer - New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM Testbench Development Functional Verification
Formal Verification Engineer - New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog Formal Methods Property Checking RTL Verification
Design Verification Engineer — PCIe Protocol IP (Silicon Patterns)
Verification
PCIe UVM SystemVerilog Protocol Verification IP Verification
Physical Design Engineer — Advanced Node SoC (Altera)
Physical Design
Place & Route Timing Closure Floorplanning CTS STA
Lead Physical Design Engineer — AI NPU (NXP Semiconductors)
Physical Design
Physical Design Flow P&R Timing AI/NPU Architecture ICC2
Senior ASIC RTL Integration and Netlisting Engineer (NVIDIA)
RTL Design
SystemVerilog ASIC Design RTL Coding Logic Synthesis Timing Analysis
Physical Design Engineer — STA, CTS & Signoff (7Rays Semiconductors)
✅ Fresher FriendlyPhysical Design
Static Timing Analysis Cadence Tempus Synopsys PrimeTime CTS Physical Design ECO
DFT Engineer — ASIC IP Verification (AMD)
DFT
ATPG JTAG Scan Insertion UVM VCS Synopsys DFT Compiler Mentor Tessent
Physical Design Engineer Sr Lead — Advanced Node SoC (Qualcomm)
Physical Design
Cadence Innovus STA CTS Floorplanning Power Optimization Deep Submicron ECO
IP Design Verification Engineer — UVM, SoC & Embedded Processors (Texas Instruments)
Verification
SystemVerilog UVM SoC Verification Embedded Processors Functional Coverage Tcl
Principal Engineer — ASIC Pre-Silicon Validation HAPS Prototyping (Micron Technology)
Verification
HAPS Prototyping ZeBu Emulation Pre-Silicon Validation C++ Python DRAM Architecture
SOC/FPGA Design Verification Engineering Lead — Intel Altera (Altera)
FPGA
SystemVerilog UVM FPGA Verification Intel Quartus Protocol Verification SoC Debug
VLSI Engineer — Digital Design & RTL Verification (VLSI FOR ALL)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog VLSI Design Digital Logic EDA Tools RTL Simulation
Verification Engineer — Formal Automation & Property Checking (Iravan Technologies)
✅ Fresher FriendlyVerification
Formal Verification JasperGold SVA Property Specification SystemVerilog Cadence Jasper
Senior ASIC Design Engineer — RTL & Synthesis (NVIDIA)
RTL Design
SystemVerilog Verilog RTL Design Logic Synthesis STA CDC/RDC DFT
Hardware System Engineer — iPhone System Technologies SoC (Apple)
SoC Architecture
C/C++ Python SoC Debug System Architecture Hardware-Software Integration Silicon Validation
Power-Aware SoC Verification Engineer — Entry Level (Chip Smart Technologies)
✅ Fresher FriendlySoC Architecture
SoC Verification UPF Power Domains Low Power Design SystemVerilog UVM
Senior Design Verification Engineer — SoC (MediaTek)
Verification
SystemVerilog UVM Functional Verification SoC Verification Coverage-Driven Verification
DFT Engineer — ASIC Test Architecture (Texas Instruments India)
DFT
DFT Scan Insertion ATPG MBIST JTAG Boundary Scan Silicon Test
Design Verification Engineer — PCIe Protocol IP (Silicon Patterns)
Verification
PCIe SystemVerilog UVM Protocol Verification Constrained Random Functional Coverage
Physical Design Engineer — Full Flow RTL to GDSII (Quest Global)
Physical Design
Physical Design Floorplanning Placement & Route CTS Timing Closure Synopsys ICC2
Physical Design Engineer — FPGA Timing & Floorplan (Altera)
FPGA
FPGA Physical Design Timing Closure CTS Quartus Prime Intel EDA Tools PnR
VLSI Design & Development Engineer — Entry Level (Nxfee Innovation)
✅ Fresher FriendlyRTL Design
VLSI Design Verilog Digital Design FPGA Logic Design Synthesis
Design Verification Engineer — Entry Level (SingleFocus Labs)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verilog Testbench Development Digital Design Simulation
ASIC Design Engineer — Circuits, AI GPU (NVIDIA AI)
AI Silicon
ASIC Design Circuit Design Analog/Mixed-Signal Timing Analysis SPICE Simulation
Staff Design Verification Engineer — SerDes & AMS IPs (Marvell Technology)
Verification
SystemVerilog UVM SerDes Verification Mixed-Signal Simulation AMS Protocol Verification
DFT Engineer — Automotive Grade SoC (NXP Semiconductors)
DFT
DFT ATPG Boundary Scan BIST Automotive ASIC In-Vehicle Networking
Sr Physical Design Engineer — Advanced Node ASIC (Synopsys)
Physical Design
Place & Route STA ECO Floorplanning CTS Synopsys ICC2 Primetime
System-on-Chip Design Engineer — RTL & Integration (Mirafra Technologies)
RTL Design
RTL Design SystemVerilog ASIC Design SoC Integration UVM Formal Verification
Graduate Engineer Trainee — FPGA Design (Yuktha Innovation)
✅ Fresher FriendlyFPGA
FPGA Verilog VHDL RTL Design Xilinx Intel FPGA Digital Design
VLSI Engineer I — Entry Level Design & Verification (Hewlett Packard Enterprise)
✅ Fresher FriendlyVerification
VLSI Design Verification Verilog Digital Logic ASIC Fundamentals EDA Tools
Design Verification Engineer — IP & SoC Level (Interex Semiconductor)
✅ Fresher FriendlyVerification
SystemVerilog UVM Testbench Development SoC Verification ECE/VLSI
SOC Design Engineer — RTL Integration & Chip Frontend (NVIDIA)
SoC Architecture
RTL Integration SystemVerilog SoC Architecture Netlist Padring Design
Wireless SoC Design Engineer — MAC & ASIC Integration (Apple)
SoC Architecture
ASIC Design SoC Integration RTL Design Verilog SystemVerilog Wireless MAC
Senior DFT Design Engineer — Silicon Bring-up (AMD)
DFT
DFT ATPG Scan Insertion JTAG Silicon Bring-up Pattern Debug
Silicon Design Verification Engineer — TPU, Google Cloud (Google)
AI Silicon
SystemVerilog UVM Python RTL Design SoC Verification ASIC DV
DFT Principal Engineer — Advanced SoC Test (onsemi)
DFT
DFT Scan MBIST LBIST JTAG ATPG Tessent Verilog
Systems Architecture Intern — SoC Design (STMicroelectronics)
✅ Fresher FriendlySoC Architecture
Digital Design ARM Cortex SoC Architecture Verilog EDA Tools
Analog Layout Engineer — Entry Level (Modernize Chip Solutions)
✅ Fresher FriendlyPhysical Design
Analog Layout CMOS Cadence Virtuoso DRC LVS Semiconductor Devices
VLSI/Embedded Engineer — Entry Level (ChipSol)
✅ Fresher FriendlyVLSI Design
VLSI Design Verilog Embedded Systems Digital Electronics C/C++
Design Verification Engineer — Silicon and Systems Group (Amazon)
Verification
SystemVerilog UVM Verification Methodology Python AMBA Protocols
Staff ASIC Design Engineer — Networking SoC (Nokia)
RTL Design
Verilog SystemVerilog RTL Design Synthesis Lint CDC Low Power Design
Physical Design Engineer — RTL to GDSII Implementation (TCS)
Physical Design
Physical Design Floorplanning PnR STA Cadence Innovus ICC2 PrimeTime
RTL Engineer — Analog & Mixed Signal SoC (Texas Instruments)
RTL Design
Verilog RTL Design Synthesis Lint CDC Low Power UPF
ASIC Design for Testability Engineer — Silicon (Google)
DFT
DFT Scan Insertion ATPG MBIST JTAG Verilog Python
Senior AI Chip Design Engineer — ASIC Methodologies (NVIDIA)
AI Silicon
Verilog SystemVerilog ASIC Design Python TCL Synthesis STA
VLSI Engineer — Entry Level (VLSI FOR ALL Pvt Limited)
✅ Fresher FriendlyRTL Design
VLSI Design Digital Logic Verilog SystemVerilog ASIC Fundamentals
Staff ASIC Physical Design Engineer (Micron Technology)
Physical Design
ASIC Physical Design P&R CTS STA Power Analysis Advanced Nodes DRC/LVS
DFT Engineer — Silicon Development Group (Tesla)
DFT
DFT Scan Chain BIST ATPG JTAG Synopsys DFT Compiler SoC Tapeout
ASIC RTL Design Engineer — Sr (Qualcomm)
RTL Design
RTL Design SystemVerilog Micro-architecture Synthesis STA IP Cores
SoC Design Verification Engineer (Apple)
Verification
UVM SystemVerilog Computer Architecture Networking Protocol Python
Physical Design Engineer — Advanced Node SoC (MediaTek)
Physical Design
Cadence Innovus Floorplan P&R CTS STA Physical Implementation Advanced Node
Lead Product Engineer — Digital Implementation EDA (Cadence)
EDA Tools
Digital Implementation VLSI Physical Design Timing Analysis EDA Tools Cadence Innovus
Senior Applications Engineer — Verification EDA (Synopsys)
✅ Fresher FriendlyEDA Tools
Digital Verification UVM SystemVerilog EDA Simulation Tools Customer Support
Verification Engineer — AI SoC & GPU Silicon (NVIDIA)
Verification
SystemVerilog UVM Python C++ Simulation Debug Lint/CDC
Power Methodology and Modeling Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyAI Silicon
Power Analysis ML/AI RTL Design Chip Design Flow Python
RTL Design Lead — CPU Team (AMD)
RTL Design
Verilog SystemVerilog RTL Design CPU Architecture Synthesis Perl
Silicon Physical Design Engineer II — Google Cloud (Google)
Physical Design
Innovus ICC2 Place and Route Floorplanning STA Timing Closure
Staff Design Verification Engineer — Power Management (Renesas Electronics)
Verification
SystemVerilog UVM Power Management IC Formal Verification Assertion-Based Verification
Senior Staff Engineer — DFT (Marvell Technology)
DFT
DFT ATPG Scan Insertion BIST TestKompress SynTest
Senior Applications Engineer — EDA Physical Implementation (Synopsys)
EDA Tools
Fusion Compiler Design Compiler ICC2 Place and Route STA Tcl
SoC Physical Design Clocking Engineer (Intel)
SoC Architecture
CTS Clock Tree Synthesis STA ICC2 Place and Route Timing Constraints
FPGA Design Engineer — Defense & Aerospace (HuntingCube)
FPGA
FPGA Verilog VHDL Xilinx Vivado Intel Quartus RTL Design
RTL Design Engineer — Entry Level (IndieSemiC)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design Digital Logic AMBA Protocols
Design Verification Engineer — Entry Level (SocBridge Semiconductors)
✅ Fresher FriendlyVerification
SystemVerilog UVM Digital Logic Verilog Simulation
Engineering Intern — EDA & Silicon Design (Synopsys India)
✅ Fresher FriendlyEDA Tools
EDA Tools Digital Design SystemVerilog Python Linux
Debug Tools SoC Design Engineer (Apple)
SoC Architecture
SoC Architecture SystemVerilog JTAG Debug Protocols C++
SoC Security Engineer — Platform Architecture (Apple)
SoC Architecture
Hardware Security SoC Design Cryptography SystemVerilog Python
Senior FPGA Engineer (Arm)
FPGA
FPGA Design Vivado Verilog VHDL High-Speed Protocol Design
SoC Architect (NXP Semiconductors)
SoC Architecture
SoC Architecture Microcontroller Design SystemVerilog ASIC Flow
AI ML Engineer (Qualcomm)
AI Silicon
Deep Learning TensorFlow PyTorch AI Algorithms Python Hardware Optimization
DFT Engineer (Texas Instruments India)
DFT
DFT Architecture Scan Design ATPG Boundary Scan SystemVerilog
VLSI Engineer L3 (Wipro)
RTL Design
VLSI Design RTL Design SystemVerilog Verification Synthesis
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyASIC Design
SystemVerilog Verilog ASIC Design RTL Design Logic Synthesis DFT Timing Analysis
ASIC Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verification Python Formal Methods
ASIC RTL Integration and Netlisting Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog RTL Design Logic Synthesis Netlist Integration Perl
ASIC Physical Design Apprenticeship (Synopsys India)
✅ Fresher FriendlyPhysical Design
Physical Design Place & Route ICC2 PrimeTime Timing Closure
Senior DFT Engineer — Advanced Nodes (NXP Semiconductors)
DFT
DFT Scan Architecture MBIST BIST Design Process Variation
SoC Full Chip DV Engineer (Apple)
Verification
SystemVerilog UVM Full-Chip Verification GPU AI Accelerator
IP Logic Design Engineer — PCIe/UCIe (Intel)
RTL Design
RTL Design Verilog Microarchitecture PCIe System Integration
STA Engineer (Qualcomm India)
Physical Design
Static Timing Analysis PrimeTime Timing Closure Advanced Nodes
Sr Physical Design Engineer (Synopsys Noida)
Physical Design
Physical Design RTL-to-GDS ICC2 Power Performance Area Optimization
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design ASIC Design Flow Synthesis
Senior DFT Engineer — Memory/GPU SoC (AMD)
DFT
DFT Architecture ATPG Scan Insertion TestGen SoC Design
Staff Engineer — Design Verification (Micron Technology)
Verification
UVM Design Verification Formal Methods Memory IP Testbenches
Senior Design Verification Engineer — AI SoC (Google)
Verification
SystemVerilog UVM Design Verification Python Machine Learning SoC
STA Engineer (Qualcomm)
Physical Design
Static Timing Analysis PrimeTime PathMill Block-level STA Signoff
SoC Full Chip DV Engineer (Apple)
Verification
SystemVerilog Full-Chip Verification UVM Power Analysis Performance
ASIC Design Verification Engineer — New College Grad (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog Verilog Testbench Development Verification Methodology
VLSI Engineer L3 — Design Verification (Wipro)
✅ Fresher FriendlyVerification
SystemVerilog UVM Python Design Verification Testbench Development
Staff Engineer — Design Verification (Micron Technology)
Verification
SystemVerilog Memory Interface Verification UVM Formal Methods
Senior Design Verification Engineer — GPU SoC (Mythic)
AI Silicon
SystemVerilog UVM GPU Verification Deep Learning Inference
Senior DFT Engineer — GPU SoC (AMD)
DFT
DFT BIST Scan Architecture Test Compression ATPG
Sr Physical Design Engineer (Synopsys)
Physical Design
Place & Route Timing Analysis STA ICC Innovus Power Analysis
Senior Design Verification Engineer — Silicon Cloud (Google)
Verification
SystemVerilog UVM Formal Verification Python RTL
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog ASIC Design Flow RTL Design Synthesis DFT
FPGA Design Engineer — Aerospace & Defense Systems (HCL Tech)
FPGA
FPGA Xilinx Vivado VHDL Verilog Timing Closure DO-254
Junior Verification Engineer — Memory Controller IP (Samsung R&D India)
✅ Fresher FriendlyVerification
SystemVerilog UVM LPDDR5 AXI Protocol Assertion-Based Verification
Graduate Engineer Trainee — RTL Verification (MediaTek India)
✅ Fresher FriendlyVerification
SystemVerilog UVM basics Digital Design Verilog Python
VLSI Design Intern — RF & mmWave Transceiver (Qualcomm India)
✅ Fresher FriendlyAnalog/RF Design
Analog Design RF Circuits Cadence Virtuoso Spectre MATLAB
EDA Application Engineer — Virtuoso Custom Layout & AMS (Cadence)
EDA Tools
Cadence Virtuoso Spectre AMS Simulation SKILL scripting DRC/LVS
AI Silicon Engineer — LPU Compute Architecture (Groq)
AI Silicon
Microarchitecture LLVM Compiler-Hardware Co-design RTL Python
Senior DFT Engineer — GPU SoC Scan & BIST (AMD)
DFT
DFT Scan Insertion ATPG BIST Tessent Mentor FASTSCAN
SoC Architecture Engineer — Neural Engine & AI Accelerator (Apple)
SoC Architecture
SoC Architecture Microarchitecture AI/ML Accelerators Performance Modeling C++
Physical Design Engineer — EMIB Advanced Packaging (Intel)
Physical Design
Floorplanning Placement Routing PrimeTime Calibre Advanced Packaging
Senior RTL Design Engineer — GPU Architecture (NVIDIA)
RTL Design
SystemVerilog RTL Design Microarchitecture Python RISC-V
ASIC Design Engineer (Circuits) — NVIDIA
AI Silicon
Staff Engineer — RTL Design — NXP Semiconductors
RTL Design
Sr Staff Formal Verification R&D Engineer — Synopsys
AI for EDA
Principal ASIC Physical Design Engineer — Synopsys
Physical Design
RTL Design Engineer — Sr. Lead — Qualcomm
RTL Design
Senior Design Verification Engineer — NXP Semiconductors
Verification
Design Verification Engineer — PravegaSemi PVT LTD
✅ Fresher FriendlyVerification
RTL Design Engineer — BOLTCHIP
RTL Design
DFT Engineer — BigEndian Semiconductors
✅ Fresher FriendlyDFT/Test
Digital Engineer — Texas Instruments India
✅ Fresher FriendlyRTL Design
Junior Verification Engineer — Mixed-Signal IP (Analog Devices India)
✅ Fresher FriendlyVerification
SystemVerilog UVM Basics Testbench Development Analog IP Verification Python
Graduate Engineer Trainee — VLSI RTL Design (Wipro VLSI)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog Digital Design Logic Synthesis Questa/ModelSim
FPGA Design Intern — Automotive SoC (STMicroelectronics India)
✅ Fresher FriendlyFPGA
FPGA Verilog/VHDL Xilinx/Intel FPGA Tools Digital Design Basics Simulation
EDA Application Engineer — Calibre DRC/LVS Signoff (Siemens EDA)
EDA Tools
Calibre DRC LVS ERC Python Tcl Physical Verification Customer Support
Analog Mixed-Signal Design Engineer — Power Management (Texas Instruments India)
Analog/Mixed-Signal
Analog Circuit Design SPICE Simulation Op-Amps ADC/DAC Cadence Virtuoso Layout
Memory Interface Verification Engineer (Micron Technology)
Verification
SystemVerilog UVM DDR5 LPDDR5 Memory Protocols Python Assertions
RTL Design Engineer — Storage Controller SoC (Marvell)
RTL Design
SystemVerilog RTL Design Microarchitecture NVMe PCIe CDC Analysis
Senior DFT Engineer — Networking SoC (Broadcom)
DFT
DFT Architecture ATPG Scan Insertion MBIST Tessent Boundary Scan
Physical Design Engineer — Advanced Node 3nm/2nm (ARM)
Physical Design
Floorplanning Place & Route STA Clock Tree Synthesis Innovus PrimeTime
AI Silicon Architect — TPU/LLM Accelerator Design (Google DeepMind)
AI Silicon
SoC Architecture RISC-V AI Accelerators RTL Design Performance Modeling Python
Senior Physical Design Engineer — Advanced Packaging & Chiplets
Physical Design
Innovus Floorplanning CTS Power Grid 3DIC HBM Signoff
AI Silicon Architect — LLM Accelerator Design
AI Silicon
SoC Architecture LLM Inference NoC Design Memory Subsystems RISC-V C++
EDA Tools Engineer — Static Timing Analysis & Signoff
EDA Tools
PrimeTime STA Tcl Python SPICE Liberty SDC Timing Closure
SoC Integration & Architecture Engineer — Mobile Platform
SoC Architecture
SoC Architecture ARM AMBA AXI Cache Coherency Power Management C++
Photonics Integration Engineer — Silicon Photonics
Photonics
Silicon Photonics Optical Modulator PDK Layout Python FDTD Simulation
VLSI Design Intern — Analog Mixed-Signal (Fresher)
✅ Fresher FriendlyRTL Design
CMOS Design Analog Layout Cadence Virtuoso SPICE Verilog-AMS
DFT Intern — Scan Insertion & ATPG (Fresher)
✅ Fresher FriendlyDFT
DFT ATPG Tessent JTAG Boundary Scan Verilog Python
Junior Verification Engineer — Digital SoC (Fresher)
✅ Fresher FriendlyVerification
SystemVerilog UVM Functional Coverage Assertions Python Git
RTL Design Engineer — GPU Compute Architecture
RTL Design
SystemVerilog RTL Design UVM Python Synthesis Timing Closure
FPGA Design Engineer — Data Center Acceleration
FPGA
FPGA Verilog HLS OpenCL PCIe DRAM Interfaces Vivado
Groq
DFT Engineer — AI Accelerator Chips
DFT
ATPG MBIST Scan Compression Tessent Design Compiler JTAG
Qualcomm
Graduate VLSI Design Engineer — Fresher
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog Digital Design CMOS fundamentals VLSI
Texas Instruments
Verification Intern — Chip Verification (Entry Level)
✅ Fresher FriendlyVerification
SystemVerilog UVM basics Python Scripting RISC-V architecture
NVIDIA
Senior Verification Engineer — AI SoC
AI Silicon
SystemVerilog UVM Formal Verification Assertion-Based Verification Python
Apple Silicon
Physical Design Engineer — 5nm/3nm ASIC
Physical Design
Innovus Tempus Calibre TCL scripting STA Low-Power Design