Jobs Archive
Browse 3 months of semiconductor & AI roles • Sort by date, experience, or package
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Debug Tools SoC Design Engineer (Apple)
SoC Architecture
SoC Architecture SystemVerilog JTAG Debug Protocols C++
SoC Security Engineer — Platform Architecture (Apple)
SoC Architecture
Hardware Security SoC Design Cryptography SystemVerilog Python
Senior FPGA Engineer (Arm)
FPGA
FPGA Design Vivado Verilog VHDL High-Speed Protocol Design
SoC Architect (NXP Semiconductors)
SoC Architecture
SoC Architecture Microcontroller Design SystemVerilog ASIC Flow
AI ML Engineer (Qualcomm)
AI Silicon
Deep Learning TensorFlow PyTorch AI Algorithms Python Hardware Optimization
DFT Engineer (Texas Instruments India)
DFT
DFT Architecture Scan Design ATPG Boundary Scan SystemVerilog
VLSI Engineer L3 (Wipro)
RTL Design
VLSI Design RTL Design SystemVerilog Verification Synthesis
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyASIC Design
SystemVerilog Verilog ASIC Design RTL Design Logic Synthesis DFT Timing Analysis
ASIC Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verification Python Formal Methods
ASIC RTL Integration and Netlisting Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog RTL Design Logic Synthesis Netlist Integration Perl
ASIC Physical Design Apprenticeship (Synopsys India)
✅ Fresher FriendlyPhysical Design
Physical Design Place & Route ICC2 PrimeTime Timing Closure
Senior DFT Engineer — Advanced Nodes (NXP Semiconductors)
DFT
DFT Scan Architecture MBIST BIST Design Process Variation
SoC Full Chip DV Engineer (Apple)
Verification
SystemVerilog UVM Full-Chip Verification GPU AI Accelerator
IP Logic Design Engineer — PCIe/UCIe (Intel)
RTL Design
RTL Design Verilog Microarchitecture PCIe System Integration
STA Engineer (Qualcomm India)
Physical Design
Static Timing Analysis PrimeTime Timing Closure Advanced Nodes
Sr Physical Design Engineer (Synopsys Noida)
Physical Design
Physical Design RTL-to-GDS ICC2 Power Performance Area Optimization
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design ASIC Design Flow Synthesis
Senior DFT Engineer — Memory/GPU SoC (AMD)
DFT
DFT Architecture ATPG Scan Insertion TestGen SoC Design
Staff Engineer — Design Verification (Micron Technology)
Verification
UVM Design Verification Formal Methods Memory IP Testbenches
Senior Design Verification Engineer — AI SoC (Google)
Verification
SystemVerilog UVM Design Verification Python Machine Learning SoC
STA Engineer (Qualcomm)
Physical Design
Static Timing Analysis PrimeTime PathMill Block-level STA Signoff
SoC Full Chip DV Engineer (Apple)
Verification
SystemVerilog Full-Chip Verification UVM Power Analysis Performance
ASIC Design Verification Engineer — New College Grad (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog Verilog Testbench Development Verification Methodology
VLSI Engineer L3 — Design Verification (Wipro)
✅ Fresher FriendlyVerification
SystemVerilog UVM Python Design Verification Testbench Development
Staff Engineer — Design Verification (Micron Technology)
Verification
SystemVerilog Memory Interface Verification UVM Formal Methods
Senior Design Verification Engineer — GPU SoC (Mythic)
AI Silicon
SystemVerilog UVM GPU Verification Deep Learning Inference
Senior DFT Engineer — GPU SoC (AMD)
DFT
DFT BIST Scan Architecture Test Compression ATPG
Sr Physical Design Engineer (Synopsys)
Physical Design
Place & Route Timing Analysis STA ICC Innovus Power Analysis
Senior Design Verification Engineer — Silicon Cloud (Google)
Verification
SystemVerilog UVM Formal Verification Python RTL
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog ASIC Design Flow RTL Design Synthesis DFT
FPGA Design Engineer — Aerospace & Defense Systems (HCL Tech)
FPGA
FPGA Xilinx Vivado VHDL Verilog Timing Closure DO-254
Junior Verification Engineer — Memory Controller IP (Samsung R&D India)
✅ Fresher FriendlyVerification
SystemVerilog UVM LPDDR5 AXI Protocol Assertion-Based Verification
Graduate Engineer Trainee — RTL Verification (MediaTek India)
✅ Fresher FriendlyVerification
SystemVerilog UVM basics Digital Design Verilog Python
VLSI Design Intern — RF & mmWave Transceiver (Qualcomm India)
✅ Fresher FriendlyAnalog/RF Design
Analog Design RF Circuits Cadence Virtuoso Spectre MATLAB
EDA Application Engineer — Virtuoso Custom Layout & AMS (Cadence)
EDA Tools
Cadence Virtuoso Spectre AMS Simulation SKILL scripting DRC/LVS
AI Silicon Engineer — LPU Compute Architecture (Groq)
AI Silicon
Microarchitecture LLVM Compiler-Hardware Co-design RTL Python
Senior DFT Engineer — GPU SoC Scan & BIST (AMD)
DFT
DFT Scan Insertion ATPG BIST Tessent Mentor FASTSCAN
SoC Architecture Engineer — Neural Engine & AI Accelerator (Apple)
SoC Architecture
SoC Architecture Microarchitecture AI/ML Accelerators Performance Modeling C++
Physical Design Engineer — EMIB Advanced Packaging (Intel)
Physical Design
Floorplanning Placement Routing PrimeTime Calibre Advanced Packaging
Senior RTL Design Engineer — GPU Architecture (NVIDIA)
RTL Design
SystemVerilog RTL Design Microarchitecture Python RISC-V
ASIC Design Engineer (Circuits) — NVIDIA
AI Silicon
Staff Engineer — RTL Design — NXP Semiconductors
RTL Design
Sr Staff Formal Verification R&D Engineer — Synopsys
AI for EDA
Principal ASIC Physical Design Engineer — Synopsys
Physical Design
RTL Design Engineer — Sr. Lead — Qualcomm
RTL Design
Senior Design Verification Engineer — NXP Semiconductors
Verification
Design Verification Engineer — PravegaSemi PVT LTD
✅ Fresher FriendlyVerification
RTL Design Engineer — BOLTCHIP
RTL Design
DFT Engineer — BigEndian Semiconductors
✅ Fresher FriendlyDFT/Test
Digital Engineer — Texas Instruments India
✅ Fresher FriendlyRTL Design
Junior Verification Engineer — Mixed-Signal IP (Analog Devices India)
✅ Fresher FriendlyVerification
SystemVerilog UVM Basics Testbench Development Analog IP Verification Python
Graduate Engineer Trainee — VLSI RTL Design (Wipro VLSI)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog Digital Design Logic Synthesis Questa/ModelSim
FPGA Design Intern — Automotive SoC (STMicroelectronics India)
✅ Fresher FriendlyFPGA
FPGA Verilog/VHDL Xilinx/Intel FPGA Tools Digital Design Basics Simulation
EDA Application Engineer — Calibre DRC/LVS Signoff (Siemens EDA)
EDA Tools
Calibre DRC LVS ERC Python Tcl Physical Verification Customer Support
Analog Mixed-Signal Design Engineer — Power Management (Texas Instruments India)
Analog/Mixed-Signal
Analog Circuit Design SPICE Simulation Op-Amps ADC/DAC Cadence Virtuoso Layout
Memory Interface Verification Engineer (Micron Technology)
Verification
SystemVerilog UVM DDR5 LPDDR5 Memory Protocols Python Assertions
RTL Design Engineer — Storage Controller SoC (Marvell)
RTL Design
SystemVerilog RTL Design Microarchitecture NVMe PCIe CDC Analysis
Senior DFT Engineer — Networking SoC (Broadcom)
DFT
DFT Architecture ATPG Scan Insertion MBIST Tessent Boundary Scan
Physical Design Engineer — Advanced Node 3nm/2nm (ARM)
Physical Design
Floorplanning Place & Route STA Clock Tree Synthesis Innovus PrimeTime
AI Silicon Architect — TPU/LLM Accelerator Design (Google DeepMind)
AI Silicon
SoC Architecture RISC-V AI Accelerators RTL Design Performance Modeling Python
Senior Physical Design Engineer — Advanced Packaging & Chiplets
Physical Design
Innovus Floorplanning CTS Power Grid 3DIC HBM Signoff
AI Silicon Architect — LLM Accelerator Design
AI Silicon
SoC Architecture LLM Inference NoC Design Memory Subsystems RISC-V C++
EDA Tools Engineer — Static Timing Analysis & Signoff
EDA Tools
PrimeTime STA Tcl Python SPICE Liberty SDC Timing Closure
SoC Integration & Architecture Engineer — Mobile Platform
SoC Architecture
SoC Architecture ARM AMBA AXI Cache Coherency Power Management C++
Photonics Integration Engineer — Silicon Photonics
Photonics
Silicon Photonics Optical Modulator PDK Layout Python FDTD Simulation
VLSI Design Intern — Analog Mixed-Signal (Fresher)
✅ Fresher FriendlyRTL Design
CMOS Design Analog Layout Cadence Virtuoso SPICE Verilog-AMS
DFT Intern — Scan Insertion & ATPG (Fresher)
✅ Fresher FriendlyDFT
DFT ATPG Tessent JTAG Boundary Scan Verilog Python
Junior Verification Engineer — Digital SoC (Fresher)
✅ Fresher FriendlyVerification
SystemVerilog UVM Functional Coverage Assertions Python Git
RTL Design Engineer — GPU Compute Architecture
RTL Design
SystemVerilog RTL Design UVM Python Synthesis Timing Closure
FPGA Design Engineer — Data Center Acceleration
FPGA
FPGA Verilog HLS OpenCL PCIe DRAM Interfaces Vivado
Groq
DFT Engineer — AI Accelerator Chips
DFT
ATPG MBIST Scan Compression Tessent Design Compiler JTAG
Qualcomm
Graduate VLSI Design Engineer — Fresher
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog Digital Design CMOS fundamentals VLSI
Texas Instruments
Verification Intern — Chip Verification (Entry Level)
✅ Fresher FriendlyVerification
SystemVerilog UVM basics Python Scripting RISC-V architecture
NVIDIA
Senior Verification Engineer — AI SoC
AI Silicon
SystemVerilog UVM Formal Verification Assertion-Based Verification Python
Apple Silicon
Physical Design Engineer — 5nm/3nm ASIC
Physical Design
Innovus Tempus Calibre TCL scripting STA Low-Power Design