Today’s VLSI + AI Jobs
10 fresh roles posted daily at 8 AM IST • Curated for chip design & verification engineers
Analog & Mixed Signal Layout Engineer (Lumilens)
Photonics
Cadence Virtuoso Analog Layout Photonics
Design Engineer — Memory Design (Arm)
Memory Design
Memory Design Circuit Design Characterization
System IP RTL Design Lead (Tenstorrent)
RTL Design
RTL SoC Architecture System IP
Analog Design Engineer (Skyworks)
Analog Design
Analog IC Design Cadence Mixed-Signal
DFT Engineer (Astera Labs)
DFT
DFT Scan ATPG Digital Design
Digital Design Engineer (Texas Instruments)
RTL Design
RTL Verilog CDC FPGA
Design Verification Engineer II (Microsoft)
Verification
SystemVerilog UVM C++ Python Emulation
ASIC Engineer Intern, Implementation (Meta)
✅ Fresher FriendlyPhysical Design
RTL Verilog Python Emulation Implementation
Trainee Engineer — Analog Design (Infineon)
✅ Fresher FriendlyAnalog Design
Analog Design Cadence Virtuoso Monte Carlo Simulation
Silicon Engineer, Platform and Devices — University Graduate 2026 (Google)
✅ Fresher FriendlySoC Architecture
SoC Verilog Digital Design Verification