Today’s VLSI + AI Jobs
10 fresh roles posted daily at 8 AM IST • Curated for chip design & verification engineers
IP Development Engineer — RTL & Digital IP Design (Intel)
✅ Fresher FriendlyRTL Design
RTL Design SystemVerilog Verilog IP Development ASIC Flows Cadence or Synopsys EDA
Associate Engineer — DFT, Snapdragon Platform (Qualcomm)
✅ Fresher FriendlyDFT
DFT ATPG JTAG Scan Chain SystemVerilog VLSI Fundamentals
Senior Principal Engineer — Verification, High-Speed Networking SoC (Marvell Technology)
Verification
SystemVerilog UVM Formal Verification OVM Python SoC Integration Verification
SoC Architect — ARM Cortex & RISC-V Platform Design (Texas Instruments India)
SoC Architecture
SoC Architecture ARM Cortex RISC-V Memory Subsystems Power Management RTL PPA Optimization
Senior FPGA & Emulation Engineer — SoC Pre-Silicon Validation (Scaledge Technology)
FPGA
FPGA Hardware Emulation Xilinx Virtex Synopsys ZeBu SystemVerilog RTL Debugging
ASIC DFT Engineer — SoC Test Architecture (Cisco)
DFT
DFT ATPG MBIST Scan Insertion SystemVerilog IEEE 1149.1 SoC Design
Sr Synthesis & Implementation Engineer — Advanced ASIC SoC (NXP Semiconductors)
Physical Design
Logic Synthesis STA Physical Design Synopsys DC Compiler TCL Scripting RTL Signoff
2026 Campus Hire — Engineer HW, Snapdragon SoC (Qualcomm)
✅ Fresher FriendlyAI Silicon
RTL Design SystemVerilog Verilog VLSI Digital Design ECE Fundamentals
Senior Memory Controller Verification Engineer — HBM & GDDR SoC (NVIDIA)
Verification
SystemVerilog UVM Memory Protocols GDDR HBM Python Constrained Random Verification
ASIC Physical Design Engineer — RTL-to-GDSII GPU SoC (NVIDIA)
Physical Design
Physical Design RTL-to-GDSII Synthesis STA Cadence Innovus Synopsys ICC2 Floorplanning