Today’s VLSI + AI Jobs

10 fresh roles posted daily at 8 AM IST • Curated for chip design & verification engineers

Applications Engineering, Staff Engineer — Physical Verification (Synopsys)
EDA Tools
📍 Bengaluru, Karnataka, India
🎓 5–9 Years
💼 Full-time
💰 Competitive
Physical Verification EDA Tools DRC/LVS Customer Support
Physical Design Engineer — Entry Level (Digicomm Semiconductor)
✅ Fresher FriendlyPhysical Design
📍 Bengaluru, Karnataka, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 Competitive
Physical Design PnR STA Basics VLSI Fundamentals
Engineer II, Physical Design — Cores (SiFive)
✅ Fresher FriendlyPhysical Design
📍 Bengaluru, Karnataka, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 Competitive
Physical Design ASIC Flows Scripting
Engineer I — Digital IP Design & Verification (SiFive)
✅ Fresher FriendlyRTL Design
📍 Bengaluru, Karnataka, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 Competitive
RTL Design Verification VLSI CPU/SoC IPs
Physical Design Intern (SEMIFIVE)
✅ Fresher FriendlyPhysical Design
📍 Bengaluru, Karnataka, India
🎓 Internship
💼 Internship
💰 Competitive
Physical Design PnR VLSI Basics Scripting
Staff Engineer — Design Enablement (Renesas Electronics)
EDA Tools
📍 India
🎓 6–10 Years
💼 Full-time
💰 Competitive
EDA VLSI Design Enablement PDK CAD Flows
Short Term 2027 Hardware Design Engineering Intern/Co-Op (AMD)
✅ Fresher FriendlyRTL Design
📍 Markham, Ontario, Canada
🎓 Internship
💼 Internship
💰 CAD $44.5K/yr
Verilog VHDL Digital Logic VLSI Design Flow
Physical Design Lead — High Speed IPs (AMD)
Physical Design
📍 Bangalore, India
🎓 10–15 Years
💼 Full-time
💰 Competitive
Physical Design High Speed IP PnR Timing Closure
SoC Physical Design Engineer, Staff — HM PD Team (Qualcomm)
Physical Design
📍 Noida, India
🎓 8–10 Years
💼 Full-time
💰 Competitive
Physical Design PnR STA Floorplanning
Senior ASIC Verification Engineer — GPU (NVIDIA)
Verification
📍 Santa Clara, CA, USA
🎓 5–9 Years
💼 Full-time
💰 $136K–218.5K/yr
SystemVerilog UVM ASIC Verification GPU Architecture
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