Today’s VLSI + AI Jobs
10 fresh roles posted daily at 8 AM IST • Curated for chip design & verification engineers
FPGA Design Engineer — Defense & Aerospace (HuntingCube)
FPGA
FPGA Verilog VHDL Xilinx Vivado Intel Quartus RTL Design
SoC Physical Design Clocking Engineer (Intel)
SoC Architecture
CTS Clock Tree Synthesis STA ICC2 Place and Route Timing Constraints
Senior Applications Engineer — EDA Physical Implementation (Synopsys)
EDA Tools
Fusion Compiler Design Compiler ICC2 Place and Route STA Tcl
Senior Staff Engineer — DFT (Marvell Technology)
DFT
DFT ATPG Scan Insertion BIST TestKompress SynTest
Staff Design Verification Engineer — Power Management (Renesas Electronics)
Verification
SystemVerilog UVM Power Management IC Formal Verification Assertion-Based Verification
Silicon Physical Design Engineer II — Google Cloud (Google)
Physical Design
Innovus ICC2 Place and Route Floorplanning STA Timing Closure
RTL Design Lead — CPU Team (AMD)
RTL Design
Verilog SystemVerilog RTL Design CPU Architecture Synthesis Perl
RTL Design Engineer — Entry Level (IndieSemiC)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design Digital Logic AMBA Protocols
Design Verification Engineer — Entry Level (SocBridge Semiconductors)
✅ Fresher FriendlyVerification
SystemVerilog UVM Digital Logic Verilog Simulation
Engineering Intern — EDA & Silicon Design (Synopsys India)
✅ Fresher FriendlyEDA Tools
EDA Tools Digital Design SystemVerilog Python Linux