Today’s VLSI + AI Jobs

10 fresh roles posted daily at 8 AM IST • Curated for chip design & verification engineers

Associate Engineer — Systems Design Engineering, NAND Storage (SanDisk)
✅ Fresher FriendlySoC Architecture
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹8–15 LPA
Systems Engineering NAND Storage Digital Design Python Hardware Validation
Digital Logic Design Apprenticeship — ASIC & RTL (Synopsys)
✅ Fresher FriendlyRTL Design
📍 Bengaluru, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹6–12 LPA
Digital Logic Design Verilog SystemVerilog RTL Fundamentals ASIC Flows
Hardware Design Intern — FPGA Digital Design (Lattice Semiconductor)
✅ Fresher FriendlyFPGA
📍 Pune, India
🎓 Internship
💼 Internship
💰 Competitive
Verilog FPGA Design Digital Logic HDL Lattice Tools
SoC Security Engineer — Platform Architecture (Apple)
SoC Architecture
📍 Cupertino, CA, USA
🎓 5–9 Years
💼 Full-time
💰 $160K–230K/yr
Security Architecture SoC Design Hardware Security Cryptography SystemVerilog
High-Speed RTL Design Engineer — Memory Interface SoC (Micron)
RTL Design
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 ₹20–32 LPA
Verilog SystemVerilog RTL Design High-Speed I/O Memory Interfaces Synthesis
Lead Physical Design Engineer — CPU/GPU High-Performance IP (AMD)
Physical Design
📍 Bengaluru, India
🎓 8–12 Years
💼 Full-time
💰 ₹35–55 LPA
Physical Design Place & Route CPU/GPU IP STA Power Analysis ECO
GPU Physical Design Engineer — Snapdragon SoC (Qualcomm)
Physical Design
📍 Bengaluru, India
🎓 5–8 Years
💼 Full-time
💰 ₹25–40 LPA
Physical Design Place & Route Floorplanning CTS STA Innovus ICC2
Senior Verification Engineer — IP & SoC Platform (ARM)
Verification
📍 Bengaluru, India
🎓 3–6 Years
💼 Full-time
💰 ₹20–35 LPA
SystemVerilog UVM IP Verification SoC Verification Formal Verification
Software Engineer, Hardware Tools & Methodology — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyEDA Tools
📍 Santa Clara, CA, USA
🎓 0–2 Years (Fresher)
💼 Full-time
💰 $120K–160K/yr
Python Tcl RTL Design EDA Tools VLSI Flows Software Engineering
GPU Core Pipeline IP Verification Engineer (NVIDIA)
Verification
📍 Santa Clara, CA, USA
🎓 3–6 Years
💼 Full-time
💰 $140K–200K/yr
SystemVerilog UVM Python ASIC Verification Graphics IP
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