Today’s VLSI + AI Jobs
10 fresh roles posted daily at 8 AM IST • Curated for chip design & verification engineers
Staff Memory Circuit Design Verification Engineer — DRAM & SRAM (Micron Technology)
Verification
SRAM DRAM Memory Circuit Verification SystemVerilog UVM Custom Layout
Lead Software Engineer — EDA HDL Verification Tools (Cadence)
EDA Tools
Verilog VHDL EDA Tools C++ SystemVerilog Software Development
Principal Engineer — EDA Embedded Firmware & FPGA (Synopsys)
EDA Tools
FPGA Embedded Firmware EDA Tools C/C++ SystemVerilog Embedded C
Senior/Staff Design Verification Engineer — FPGA DV (Lattice Semiconductor)
Verification
SystemVerilog UVM Design Verification FPGA Formal Verification Coverage
Analog Design Engineer — Mixed-Signal SoC Wireless Infrastructure (Texas Instruments)
SoC Architecture
Analog Design Mixed-Signal SoC Wireless Infrastructure SPICE Cadence Virtuoso
CPU Design Verification Engineer — Snapdragon Power Management (Qualcomm)
Verification
SystemVerilog UVM Power Management Verification CPU Architecture SoC DV
SOC Design Engineer — RTL Integration & Chip Frontend (NVIDIA)
SoC Architecture
RTL Design SystemVerilog SoC Integration Padring Pinmux UPF
DFT Engineer — Entry Level ASIC Test Design (Tattvasemi Technologies)
✅ Fresher FriendlyDFT
DFT ATPG Scan Chain Boundary Scan JTAG SystemVerilog
Early Career SoC DFT Verification Engineer — m/f/d (Apple)
✅ Fresher FriendlyDFT
DFT ATPG Scan Insertion SystemVerilog Python BIST
RTL Design Engineer — Entry Level Digital Design (IndieSemiC)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design Digital Electronics FPGA CMOS