Today’s VLSI + AI Jobs

10 fresh roles posted daily at 8 AM IST • Curated for chip design & verification engineers

Semiconductor Engineer — Device Fabrication & Process (SiliconBoard)
✅ Fresher FriendlySoC Architecture
📍 Bengaluru, Karnataka, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹6–10 LPA
Semiconductor Fabrication Device Physics Equipment Maintenance Cleanroom Protocols Process Integration
Analog/Custom Layout Engineer — RF & Mixed-Signal IC (Axiro Semiconductor)
✅ Fresher FriendlyPhysical Design
📍 Bengaluru, Karnataka, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹8–14 LPA
Analog/Mixed-Signal Layout DRC LVS Parasitic Extraction ADC/DAC/PLL/LDO Layout RF Layout Techniques
Graduate Engineering Technician — Memory Manufacturing (Micron Technology)
✅ Fresher FriendlyPackaging
📍 Sanand, Gujarat, India
🎓 0–2 Years (Fresher)
💼 Full-time
💰 ₹4–7 LPA
Electro-mechanical Troubleshooting Equipment Maintenance Fab Process Support AI-enabled Process Optimization
Senior Applications Engineer — Silicon Photonics / Co-Packaged Optics (STMicroelectronics)
Photonics
📍 Santa Clara, CA, USA
🎓 5–9 Years
💼 Full-time
💰 $140K–190K/yr
Silicon Photonics PIC/EIC Design Enablement Co-Packaged Optics Pluggable Optics Foundry Customer Support
Senior Engineer — FPGA / Hardware Engineering (Qualcomm)
FPGA
📍 Bengaluru, Karnataka, India
🎓 2–5 Years
💼 Full-time
💰 ₹20–32 LPA
FPGA Digital/Analog/RF Systems Circuit Design Bring-up DSP Systems
Sr Staff Design Verification Engineer — AI Inference Silicon (d-Matrix)
AI Silicon
📍 Bengaluru, Karnataka, India
🎓 8–12 Years
💼 Full-time
💰 Competitive
UVM In-Memory Computing Architecture SystemVerilog AI Accelerator Verification
RTL Design Engineer — FPGA High-Speed Connectivity IP (AMD)
RTL Design
📍 Hyderabad, Telangana, India
🎓 3–6 Years
💼 Full-time
💰 ₹22–35 LPA
RTL Design FPGA Architecture High-Speed I/O Micro-architecture Verification Support
DFT Engineer — Scan, MBIST, ATPG (eInfochips, an Arrow Company)
DFT
📍 Bengaluru, Karnataka, India
🎓 4–7 Years
💼 Full-time
💰 ₹18–28 LPA
DFT Architecture Scan Insertion MBIST ATPG JTAG Siemens Tessent Verilog/SystemVerilog
Senior GPU Floorplan Design Engineer (NVIDIA)
Physical Design
📍 Santa Clara, CA, USA
🎓 6–10 Years
💼 Full-time
💰 $160K–230K/yr
Floorplanning Chip Area Planning Timing Closure Congestion Analysis Package Co-design
Senior ASIC Verification Engineer — Crypto/Security IP (NVIDIA)
Verification
📍 Beer Sheva, Israel
🎓 5–9 Years
💼 Full-time
💰 Competitive
SystemVerilog UVM Crypto RTL (AES RSA PQC) Micro-architecture Coverage Closure
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