Track 01 · SystemVerilog Primer

Number Literals, Sizing, and Signed Versus Unsigned

~12 min Hands-on lab 1 exercise Verilator
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01

Sized and Based Literals

A literal is a constant value you write directly in your code. You can write it plainly, like the number five, or you can write it as a sized and based literal that states exactly how many bits it occupies and in which base. The sized form names a width, then a base such as decimal, hexadecimal, or binary, then the value. Writing literals this way is how you say precisely which bits you mean, instead of leaving it to the tool to guess.

02

Unsized Literals and Their Defaults

When you write a number plainly with no size, it still has a width and a signedness under the hood; you just did not state them. A plain integer is treated as a signed value of a standard width. That is convenient, but it means a plain literal and a sized literal that look like the same number can behave differently in an expression. This is the first place constants quietly surprise people.

03

Signed Versus Unsigned

Every value is read in one of two ways. Read as unsigned, every bit adds to a positive total. Read as signed, the top bit carries a negative weight. The crucial idea: the very same bit pattern can mean two completely different numbers depending on which reading applies. A pattern of all ones is the largest positive value when read unsigned, and it is negative one when read signed. The bits do not change. Only the reading does.

04

Key Insight — The Slip That Still Simulates

Here is the trap, and it is one of the most quietly damaging bugs in real code. When you mix signed and unsigned values in one expression, the rules silently convert things, and a value you believed was negative can become a large positive. The arithmetic does not error. It computes a confident, wrong answer, and the simulation runs perfectly clean. A comparison that is obviously true can come back false. The only defence is to write every literal with the size and signedness you actually intend, and never leave signedness to chance. This lab shows you exactly how a clean looking expression lies.

Why this matters in real designs

A signed counter compared against an unsigned threshold can flip a safety interlock. The comparison compiles, the waveform traces look reasonable, and the bug ships into silicon. Signedness bugs are invisible in simulation because no tool warns you that a comparison changed meaning. This is one of the bugs that escapes every review except a careful reading of the types.

Lab Exercise
Lab — Write the Literals That Mean What You Intend

Fill in the two literals so the expression evaluates to the intended result. Use the eight-bit pattern hexadecimal FF and the value one. Run and submit. The test checks the result, and a signedness slip will show you a wrong answer that still simulated cleanly.

Grading method: structural check — the checker parses your literals for correct size and signedness. A signedness slip produces a wrong result with no engine warning.
Checking literals and signedness…
Pass
Correct. By marking both literals as signed, the pattern FF was read as negative one, the comparison was a signed comparison, and the obviously true result came out true.
The Signedness Slip
Your code compiled and ran with no error, but the answer is wrong. A literal was read as unsigned, so the pattern FF was treated as 255 instead of negative one, and a comparison that should be true came back false. The mentor below explains exactly what happened.
Engine output
AI Mentor
Compile Error
The checker found a syntax issue with your literals. Resolve the error below and resubmit.
Checker output
AI Mentor
Engine Error
Something went wrong on our end. Please try submitting again in a moment.
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