SystemVerilog gives you several families of operators, and the first skill is knowing which family you are reaching for. Arithmetic operators do math like addition and multiplication. Relational operators compare two values and return a true or false answer. Logical operators reason about whole values being true or false. Bitwise operators work on each individual bit. Reduction operators collapse an entire vector down to a single bit.
Most operator bugs come from grabbing the right idea from the wrong family.
This is the mistake that catches almost every beginner, so slow down here. A logical operator asks a true or false question about whole values: is this value nonzero and that value nonzero. A bitwise operator works bit by bit and hands you back a full pattern. They look almost the same (the logical form simply doubles the symbol) but they compute completely different things.
Two values that are each nonzero can produce a true result with the logical operator and a result of zero with the bitwise one. Same inputs, opposite answers. That is exactly the trap this lab will spring on you, on purpose.
A reduction operator takes a single vector and applies an operation across all of its bits to produce one bit. With it you can ask, in a compact way, whether any bit in a vector is set, whether every bit is set, or the parity of the bits. It is a small but powerful tool for asking a question about an entire vector at once, instead of testing bits one by one.
Two more traps complete the picture. First, precedence: operators do not all bind equally tightly, so an expression can group itself in a way you never intended. The fix is simple and free: add parentheses to state exactly how things group, and never trust your memory of the precedence table.
Second, equality: ordinary equality can return an unknown answer when unknown bits are involved, whereas case equality compares bit for bit and can detect an unknown exactly. When unknown values are in play, the equality operator you choose changes the answer you get.
Complete each expression with the correct operator. One expression needs a true or false answer about whole values; the other needs a bit by bit result. Run and submit. Swap one for the other and you will see the diverging value the engine computes.
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