Data Types, logic, bit, and the Cost of an Unknown

SystemVerilog signals come in two families. A four state type can hold four values: zero, one, unknown, and high impedance. A two state type can hold only zero and one. The type logic is four state. The type bit is two state. That single difference — whether a signal can represent an unknown — drives almost every type decision you will make in verification.

In verification you are hunting for bugs, and many bugs first appear as an unknown value: an uninitialised register, a bus nobody is driving, a reset that has not arrived yet. If your signal can hold an unknown, you can see that bug. If it cannot, the bug is invisible to you. That is why logic is the default type in a testbench: it tells you the truth, including the uncomfortable truth that something is unknown.

If logic always tells the truth, why does bit exist at all? Speed. A two state type is cheaper to simulate, and on large, hot paths where a value genuinely can never be unknown — for example a loop counter you fully control — bit can make a simulation meaningfully faster. The tradeoff is real: bit buys performance by giving up the ability to represent an unknown. Use it only where you are certain no unknown can occur.

Here is the trap. If you declare a signal bit and an unknown is driven onto it, the unknown does not raise an error. It is silently coerced to a definite value, usually zero. Your test then passes, your waveform looks clean, and the real bug — an uninitialised value that should have been caught — sails straight through. A wrong type choice does not crash. It hides. That is what makes it dangerous, and it is exactly what this lab will show you.