Your First Module and Its Signals

Every hardware design in SystemVerilog is built from modules. A module is a container: a named box that holds a piece of hardware and defines how the outside world connects to it. Everything you design later, from a simple counter to a full processor, is modules inside modules.

Learn the box first, because every later page lives inside one.

A module talks to the outside world only through its ports. A port is a signal that crosses the module boundary, and every port has a direction: an input carries a signal in, an output carries a signal out.

The port list is the contract between this module and whatever connects to it. Get the contract wrong and nothing else can connect correctly.

To declare a module you give it a name and then list its ports, and each port needs three things: a direction, a type, and a name. In this primer the type for a simple single signal is logic.

So a port is written as a direction, then logic, then a name. That is the whole pattern, repeated for every signal that crosses the boundary.

Here is the idea that trips up newcomers: a module by itself is structure, not behaviour. Declaring a module and its ports does not make anything happen. It defines what exists and how it connects, like the walls and doorways of a room, not the activity inside it.

The behaviour comes later, from the logic you place inside the module. On this page you are only building the box and its doorways. That is enough, and it is the foundation every later page assumes you already understand.