Technical deep-dives, AI+VLSI news & career advice for semiconductor engineers
A few years back, a team I consulted for was six weeks from tape-out on a large networking SoC. Their formal verification dashboard showed 98%...
Why Design for Testability Matters Design for Testability (DFT) is a critical discipline in modern chip design. Without DFT, manufactured chips cannot be efficiently tested...
Why Verification is 70% of Chip Design Effort Modern SoCs contain billions of transistors with incredibly complex functionality. Ensuring these chips work correctly before manufacturing...
The Verification Crisis in Advanced Node Design As chip complexity doubles every technology generation, traditional verification approaches are hitting a wall. Simulation-based verification takes months,...