VLSIChaps Academy · Track 01

Initial Blocks and Simulation Time

~12 min Hands-on lab 1 exercise Verilator
Page 08 of 50
01

The Initial Block

An initial block is a piece of testbench code that runs once, starting at time zero, from top to bottom. It is where you write your stimulus, the sequence of values you want to feed the design. Unlike hardware, which runs continuously, an initial block executes its statements a single time and is then finished. It is the most basic way to script what happens during a simulation, and it is where your control over time begins.

02

Delays Advance Simulated Time

Without any delays, every statement in an initial block would happen at time zero, one after another, with no time passing between them. To spread stimulus out across time, you insert a delay. A delay tells the simulator to advance simulated time by a set number of units before running the next statement. Delays are the mechanism by which you say exactly when each thing happens on the timeline.

03

Simulated Time Is Not Real Time

The time inside a simulation is not the wall clock time on your computer. A run covering a thousand units of simulated time might finish in a fraction of a real second, or take much longer, depending on how much the design has to compute. Simulated time is a model of how the hardware behaves over time, kept entirely inside the simulator. Whenever this page speaks of time, it means simulated time, the units you control with delays, not seconds on a clock.

04

Key Insight: Time Is Something You Author

Here is the shift in thinking. In a testbench, time does not simply happen to you; you author it. Every delay you write places an event at a precise moment on the simulation timeline, and the order and spacing of those events is entirely your design. Get the timing wrong and the design sees the wrong inputs at the wrong moments, producing wrong behaviour that is often blamed on the design when the fault is in the testbench. Controlling simulated time deliberately is a core testbench skill, and this lab makes you place events at exact times.

On the previous page, you wrote your first testbench and used a single small delay for propagation. Here you extend that idea: instead of one delay, you build a whole timed schedule where every event lands at a precise moment.

Lab: Drive a Signal on a Schedule

Write the timed steps of an initial block so a signal follows an exact schedule. Set the signal to zero at time zero, to one at time ten, back to zero at time twenty, then end the simulation at time thirty. A delay is written as a hash followed by a number of time units, placed before a statement. Run and submit. If your timing is off, the engine will name the event that happened at the wrong time.

Think of each delay as the gap before the next event. To make sig become one at time ten, you need ten units of delay after the time zero assignment. Each later step needs its own delay to move from one scheduled time to the next.
Compiling and simulating...
Correct. Your signal changed value at exactly the right moments, and the simulation ended on schedule. You did not just set values; you placed each one at a precise point in simulated time, which is the essence of writing stimulus.
Not quite. Your initial block ran, but an event happened at the wrong simulated time. The schedule requires each change at a specific moment, and one of your delays put an event early, late, or on top of another. The engine output and the mentor below name the event and the times.
Compile error.
Something went wrong reaching the engine. Try again in a moment.
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