Jobs Archive
Browse 3 months of semiconductor & AI roles • Sort by date, experience, or package • 20 jobs per page
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Staff Digital Verification Engineer (onsemi)
Verification
SystemVerilog UVM C++ SoC
Sr DFT Engineer (Mythic)
DFT
DFT ATPG STA Verilog Tcl
Senior Design Verification Engineer (MediaTek)
Verification
SystemVerilog UVM SoC Python
Senior SoC Design Verification Engineer, Google Cloud (Google)
Verification
SystemVerilog UVM FPGA SoC
Sr Engineer — Physical Design (SiFive)
Physical Design
Innovus Fusion Compiler RTL STA
Associate Engineer — SoC Verification, New College Graduate (Sandisk)
✅ Fresher FriendlyVerification
SystemVerilog UVM SoC Verification
GPU Logic Design / DFT Engineer — Entry Level (Intel)
✅ Fresher FriendlyDFT
DFT RTL SystemVerilog SoC
IP Design Engineer — NETC (NXP Semiconductors)
RTL Design
RTL SoC Perl Python
Senior Engineer IP Verification — Digital Design Verification (Micron)
Verification
RTL UVM SystemVerilog
Intern — IC Design (Silicon Labs)
✅ Fresher FriendlyRTL Design
IC Design SoC RTL Verilog
Design Verification Engineer (Altera)
Verification
SystemVerilog UVM PCIe FPGA Python Tcl
Staff Verification Design Engineer (Semtech)
Verification
UVM Verilog RTL Python Perl AMS
Principal DFT Engineer — Scan/ATPG (Ampere)
DFT
DFT ATPG Scan STA Verilog Tcl
Principal DFT Engineer (Synopsys)
DFT
DFT ATPG RTL STA
Principal Digital Engineer, DFT Design (Renesas Electronics)
DFT
DFT ATPG CDC RTL Verilog
Trainee Engineer — Digital Design Verification (Infineon Technologies)
✅ Fresher FriendlyVerification
SystemVerilog UVM Emulation Palladium Zebu Python
ASIC Engineer (Cisco)
SoC Architecture
ASIC Design RTL Verification
Design Verification Engineer (Analog Devices)
Verification
SystemVerilog UVM Verilog RTL Python Perl
Formal Verification Engineer — New College Graduate 2026 (NVIDIA)
✅ Fresher FriendlyVerification
Formal Verification RTL Verilog SoC
Graduate GPU Verification Engineer (Imagination Technologies)
✅ Fresher FriendlyVerification
SystemVerilog UVM C++ Python FPGA RTL
Staff SoC Design Engineer (Quadric)
SoC Architecture
SoC SystemVerilog Verilog DDR PCIe FPGA
Principal Engineer, Design — SoC Integration and RTL/IP (Microchip Technology)
RTL Design
RTL SoC Integration SystemVerilog CDC DFT STA Tcl
Memory Design Engineer (Cadence)
Analog
Memory Design Circuit Design Cadence
RTL Design Engineer, ARM (STMicroelectronics)
RTL Design
RTL SoC CDC DFT STA Python
RTL Designer, Physical AI SoC (Velaura AI)
AI Silicon
SystemVerilog RTL FPGA Emulation SoC
2027 Campus Hire, Associate Engineer, Hardware (Qualcomm)
✅ Fresher FriendlySoC Architecture
Verilog RTL DFT FPGA C++ Perl Tcl
RTL Design Engineer — Fresher (DECCANX)
✅ Fresher FriendlyRTL Design
SystemVerilog RTL CDC AXI FIFO design
Assistant Engineer — Silicon Validation (Infineon Technologies)
Verification
Silicon Validation FPGA Python Microcontrollers SoC
Emulation Engineer (Broadcom)
Verification
Palladium Zebu SystemVerilog Verilog PCIe Python Tcl
Staff Silicon Logical Design Engineer (Graphcore)
AI Silicon
SystemVerilog RTL CDC SoC Python
RTL Design Engineer, PCIe (AMD)
RTL Design
RTL PCIe SoC Verilog SystemVerilog
Principal Logic Design Engineer, UALink IP (Astera Labs)
RTL Design
SystemVerilog RTL PCIe CDC SoC
Staff Physical Design Engineer (EnCharge AI)
Physical Design
Physical Design Cadence Python AI Hardware
Senior ASIC Digital Engineer, SoC Design (Sandisk)
RTL Design
RTL SystemVerilog CDC DFT SoC
AMS Verification Engineer (Skyworks)
Verification
SystemVerilog Verilog Cadence Python AMS
Layout Engineer (Texas Instruments)
✅ Fresher FriendlyAnalog
IC Layout Mask Design Cadence Virtuoso Calibre
Engineer, Physical Design (Arm)
Physical Design
Fusion Compiler Innovus UPF Tcl Python STA
DFT Engineer (GlobalFoundries)
DFT
DFT ATPG MBIST Synopsys Cadence Python
Interim Engineering Intern, Hardware (Qualcomm)
✅ Fresher FriendlySoC Architecture
Verilog RTL DFT FPGA C++ Perl Tcl
Silicon Trainee — RTL, Verification & Implementation (DECCANX)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Verification Python
Sr. SoC Design Verification Engineer (Mettlesemi)
Verification
SystemVerilog UVM Verilog DDR SoC Verification
Senior Staff Engineer, Physical Design (TYLsemi)
Physical Design
Physical Design ICC2 Innovus STA Tcl
Logic Design Engineer (IBM)
RTL Design
RTL Microprocessor Architecture Logic Design
Staff Digital Design Engineer — MCU (NXP Semiconductors)
RTL Design
SystemVerilog Verilog RTL DFT Tcl Python
Lead Engineer — RTL Design, Wireless Modem IP (Silicon Labs)
RTL Design
RTL SystemVerilog CDC SoC
Senior Engineer, Physical Design (SiFive)
Physical Design
Physical Design Innovus Fusion Compiler RTL
ASIC Verification Engineer (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verilog C++ Python FPGA
ASIC Engineer Intern, Infra Silicon Enablement (Meta)
✅ Fresher FriendlySoC Architecture
ASIC Emulation PCIe DDR C++ Python
SRAM Design & Layout Intern (NextiCron Technologies)
✅ Fresher FriendlyAnalog
SRAM Design Circuit Design Layout VLSI
Silicon Design Verification Engineer (Intel)
Verification
SystemVerilog UVM Verilog RTL SoC
ASIC DFT Engineer (Cisco)
DFT
DFT ATPG Scan PrimeTime Tcl Python
Senior Design Verification Engineer (MediaTek)
Verification
SystemVerilog UVM SoC Verification Python
Analog Circuit Design — DC-DC Converter (Samsung Semiconductor)
Analog
Analog Circuit Design DC-DC Converter Power Management IC
PE Logic Design — PCIe IP (Rambus)
RTL Design
RTL Verilog PCIe FPGA
Design Engineer — FPGA & SoC (Altera)
FPGA
Verilog SystemVerilog RTL FPGA STA Python
ASIC Engineer Intern, Design (Meta)
✅ Fresher FriendlyRTL Design
RTL Verilog Python Perl ASIC Design
India Campus Hire — Memory Design & LPDDR Verification (Micron)
✅ Fresher FriendlyVerification
Memory Design DDR5/LPDDR5 Design Verification Analog/Mixed-Signal
Principal Engineer, DFT (Marvell)
DFT
DFT ATPG MBIST Scan STA Synopsys
Staff STA Engineer (Analog Devices)
Physical Design
STA Physical Design SoC Python Perl
Formal Verification Internship (Synopsys)
✅ Fresher FriendlyVerification
SystemVerilog Verilog Formal Verification Python Tcl
Analog Layout Engineer — Image Sensor (onsemi)
Physical Design
Virtuoso Calibre Analog Layout
Principal Engineer, Design Synthesis, LEC & CLP (Infineon Technologies)
Physical Design
Fusion Compiler UPF STA LEC Tcl
Senior Engineer II, Digital Design (Microchip Technology)
RTL Design
RTL CDC DFT Tcl Perl
SoC Edge-AI Design Verification Engineer, Google Cloud (Google)
AI Silicon
SystemVerilog UVM FPGA RTL
Emulation Verification Engineer (Ampere)
Verification
Palladium Zebu SystemVerilog C++ Python
Digital Design – PD Engineer, Career Accelerator Program (Texas Instruments)
✅ Fresher FriendlyPhysical Design
Physical Design Digital Design RTL
2027 Campus Hire — Engineer, Hardware (Qualcomm)
✅ Fresher FriendlyRTL Design
Verilog RTL DFT FPGA Tcl
DFT Engineer (Broadcom)
DFT
DFT MBIST Scan ATPG STA
DFT Engineer — Modus ATPG (Cadence)
DFT
DFT ATPG
ASIC Engineer Intern, Physical Design (Meta)
✅ Fresher FriendlyPhysical Design
RTL Verilog Python Physical Design
System-on-Chip Design Engineer (Mythic)
SoC Architecture
RTL Microarchitecture SoC Integration DFT Python
Senior SoC Design Verification Engineer (Quadric)
Verification
SystemVerilog UVM DDR PCIe Python
Design Verification Engineer — Physical AI SoC (Velaura AI)
AI Silicon
SystemVerilog UVM Formal Emulation FPGA
Senior VLSI Design Engineer (Sandisk)
RTL Design
RTL Verilog UVM
Digital Design Engineer — AI Accelerators (STMicroelectronics)
AI Silicon
RTL SystemVerilog Microarchitecture Synthesis STA
Digital Design Engineer Apprenticeship — SerDes PHY Verification (Synopsys)
✅ Fresher FriendlyVerification
Verilog SystemVerilog UVM PCIe
Design Verification Engineer — Career Accelerator Program (Texas Instruments)
✅ Fresher FriendlyVerification
RTL GLS Coverage Scripting
Engineer — Physical Design (Arm)
Physical Design
Fusion Compiler Innovus Tcl Python UPF
SoC RTL Design Engineer (Lattice Semiconductor)
RTL Design
Verilog RTL CDC FPGA SoC
ASIC Engineer Intern, Design Verification (Meta)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verilog Python
DFT Design Engineering Intern (Intel)
✅ Fresher FriendlyDFT
DFT Scan ATPG Verilog Digital Design
Power Analysis and Optimization Engineer — New College Graduate 2027 (NVIDIA)
✅ Fresher FriendlyAI Silicon
Power Analysis Low Power Design RTL Python ASIC Flow
VLSI Logic Design Intern (Hewlett Packard Enterprise)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog Logic Design ASIC Digital Design
Tech Lead, STA — AI Connectivity Silicon (Astera Labs)
Physical Design
STA PrimeTime PrimeTime SI SDC CDC Timing Signoff Tcl/Python
Entry Level DFT Design Engineer (NXP Semiconductors)
✅ Fresher FriendlyDFT
DFT Scan ATPG Verilog Digital Design
Senior Principal Engineer, SoC Design Verification (GlobalFoundries)
✅ Fresher FriendlyVerification
SystemVerilog UVM SoC Verification CPU/Subsystem Verification Python
Lead Engineer – RTL Design, Wireless Modem IP (Silicon Labs)
RTL Design
Verilog SystemVerilog RTL Design Wireless Modem IP Lint/CDC
Staff/Senior Staff Engineer, STA (Renesas Electronics)
Physical Design
STA PrimeTime Tempus SDC MMMC Timing Closure Tcl
In-Order Tile TestBench Design Verification Engineer (SiFive)
Verification
SystemVerilog UVM CPU Verification RISC-V ASIC/SoC Verification
Sr. Staff ASIC Design Engineer (Synaptics)
SoC Architecture
ASIC/SoC Design RTL Microarchitecture Verilog/SystemVerilog Low Power
ASIC Engineer — Physical Implementation (Cisco)
Physical Design
Physical Design STA PrimeTime ECO Sign-off
Physical Design Engineer (NXP Semiconductors)
Physical Design
Floorplanning Placement CTS Routing STA
Senior FPGA IP Design Engineer (Altera)
FPGA
FPGA RTL Design Verilog SystemVerilog
Staff Design Verification Engineer — DDR (Qualcomm)
Verification
UVM SystemVerilog DDR AHB/AXI ASIC Verification
Senior Staff Emulation Engineer (Marvell)
Verification
Palladium Veloce Emulation Verilog SystemVerilog
ASIC Digital Design Engineer — Entry Level (Synopsys)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design Verification
ASIC Design Engineer — Low Power, New College Grad 2027 (NVIDIA)
✅ Fresher FriendlyRTL Design
ASIC Design Low Power RTL Verilog
New College Grad — Engineer, ASIC Digital Design (Micron)
✅ Fresher FriendlyRTL Design
ASIC Digital Design RTL SystemVerilog
Associate Design Verification Engineer (Analog Devices)
✅ Fresher FriendlyVerification
SystemVerilog UVM Verilog RTL Python TCL
CPU Verification Engineer (AMD)
Verification
SystemVerilog UVM CPU Verification ASIC DV
Physical Design Engineer — Static Timing Analysis (IBM)
Physical Design
Physical Design STA Timing Closure
Engineer II — CAD (Microchip Technology)
EDA Tools
CAD EDA Flows Scripting RTL
STA Synthesis Engineer (Samsung Semiconductor India Research)
Physical Design
STA PrimeTime Tempus Timing Constraints UPF Tcl Python
PCIe Verification Engineer (Broadcom)
Verification
PCIe ASIC Verification SystemVerilog UVM
ASIC Design Engineer — Networking ASICs (Hewlett Packard Enterprise)
RTL Design
Verilog VHDL ASIC Design Synopsys Cadence
ASIC Digital Design Engineer — Formal Verification (Synopsys)
✅ Fresher FriendlyVerification
SystemVerilog SVA Formal Verification Python Tcl
New College Grad 2026 — Post Silicon Electrical Validation Engineer (Cadence)
✅ Fresher FriendlySilicon Validation
Post-Silicon Validation Electrical Validation Lab Debug Python
Design Verification Engineer — Entry Level (Texas Instruments)
✅ Fresher FriendlyVerification
SystemVerilog UVM Digital Verification
Verification Engineer — SoC Validation (Arm)
Verification
Verilog SystemVerilog SoC Validation Tcl Python
Microarchitecture and Design Engineer — AI SoC (Intel)
AI Silicon
RTL Design Microarchitecture AI SoC SystemVerilog
Analog Circuit Design Engineer (Altera)
FPGA
Analog Circuit Design Mixed-Signal IP Advanced Process Nodes
Lead Performance Modeling Engineer — GPU SoC (AMD)
AI Silicon
Performance Modeling GPU Architecture SoC C++
Staff Engineer, ASIC Gen AI (Micron)
EDA Tools
ASIC Generative AI Python Semiconductor Design Automation
Product Engineer — AI-Driven Analog Chip Design (Siemens EDA)
EDA Tools
Analog Chip Design EDA AI/ML Circuit Simulation
Senior AI Silicon Infrastructure Engineer (Microsoft)
AI Silicon
Design Verification DFT Emulation PD Handoff IP Integration
Memory Circuit Design Engineer (Qualcomm)
SoC Architecture
Memory Circuit Design SRAM Custom Layout SPICE
ASIC Engineer — Physical Design (Cisco)
Physical Design
ASIC Physical Design Floorplanning P&R STA
Physical Design Applications Engineering Engineer (Synopsys)
✅ Fresher FriendlyPhysical Design
RTL2GDS PnR Tools CMOS Fundamentals Digital Circuits ASIC Design
Associate Engineer Intern, System Design Verification (Sandisk)
✅ Fresher FriendlyVerification
Digital Electronics SystemVerilog Verification Memory Systems
NVIDIA 2027 Internship — Hardware Physical Design / VLSI
✅ Fresher FriendlyPhysical Design
Physical Design VLSI Digital Design EDA Tools
Senior/Lead Engineer – ASIC Verification (SignOff Semiconductors)
Verification
SystemVerilog UVM Verification Planning Sign-off
Lead Design Verification Engineer (Tech Mahindra)
Verification
ASIC/SoC Verification UVM PCIe SystemVerilog
Principal Engineer – SoC Physical Design (Aion Silicon)
Physical Design
SoC Physical Design Timing Closure IR Drop Congestion
Staff Engineer – Design Verification (TYLsemi)
AI Silicon
Design Verification High-speed Interconnect IP SoC UVM
Design Verification Engineer (HCLTech)
Verification
SystemVerilog UVM SoC Verification
Engineering Intern 1 (Lam Research)
✅ Fresher FriendlySemiconductor Equipment
Semiconductor Equipment Electronics Engineering Fundamentals
Graduate Engineer Trainee – Physical Design (HC Robotics)
✅ Fresher FriendlyPhysical Design
Physical Design ASIC Backend Flow Floorplanning STA VLSI
Design Verification Engineer (Digicomm Semiconductor)
Verification
SystemVerilog UVM IP/SoC Verification Debug
Principal Engineer, DFT (Renesas Electronics)
DFT
DFT ATPG MBIST RTL Integration Test Engineering
ASIC Engineer Intern, Infra Silicon Enablement (Meta)
✅ Fresher FriendlyAI Silicon
ASIC Design Verilog/SystemVerilog Digital Design Silicon Bring-up
Design Verification Engineer 2 (Lattice Semiconductor)
Verification
FPGA Verification SystemVerilog UVM SoC
Principal Physical Verification Engineer (NXP)
Physical Design
Physical Verification DRC LVS Full-chip
Principal Engineer, ASIC Physical Design (Ayar Labs)
Photonics
ASIC Physical Design Custom Circuits Photonics SoC Integration
Lead Physical Design Engineer (Quest Global)
Physical Design
Physical Design RTL Power Timing
FPGA Validation Engineer (UST)
FPGA
FPGA Validation PCIe Post-Silicon Validation
Career Accelerator Program – Digital IC Design Engineer (Texas Instruments)
✅ Fresher FriendlyRTL Design
Digital Design Verilog RTL ASIC Flow
Analog Design Engineering Intern (Cadence)
✅ Fresher FriendlyAnalog Design
Analog Circuit Design Virtuoso SPICE Simulation
Senior ASIC Design Engineer – XBAR IP (NVIDIA)
RTL Design
RTL Design Verilog SystemVerilog ASIC
ASIC RTL Design Lead (eInfochips)
RTL Design
ASIC SoC RTL Design Micro-architecture
Physical Design Engineer (Syntiant)
Physical Design
Physical Design RTL to GDSII STA Timing Closure
RTL Design Engineer (Infineon Technologies)
RTL Design
RTL Design Verilog/SystemVerilog Digital Design
Sr Engineer/Staff Engineer, CPU Core Verification (Tenstorrent)
AI Silicon
RISC-V CPU Verification SystemVerilog UVM
VLSI Engineer L3 (Wipro)
SoC Architecture
VLSI ASIC RTL Verification
RTL Design Engineer (QTIMINDS)
RTL Design
RTL Design Verilog SystemVerilog
Physical Design Engineer - Senior/Lead (MosChip)
Physical Design
Physical Design Top-level PnR Timing Closure
CPU Core Physical Design Technical Graduate Intern, Spring (Intel)
✅ Fresher FriendlyPhysical Design
Physical Design RTL2GDS PnR CMOS
Hardware Developer Intern - Austin, TX - 2027 (IBM)
✅ Fresher FriendlyFPGA
FPGA RISC-V ARM Computer Architecture
Senior SoC Verification Engineer (Arm)
Verification
SystemVerilog UVM SoC Verification Arm IPs
Senior ASIC Digital Engineer - SoC Verification (Sandisk)
Verification
SystemVerilog UVM SoC Verification
Design for Test Intern, BS - Summer 2027 (Marvell)
✅ Fresher FriendlyDFT
DFT Scan ATPG Verilog
Digital Design Senior Engineer — ASIC RTL (Synopsys)
RTL Design
ASIC RTL Verilog/SystemVerilog FSMs Synthesis
Senior Physical Design Engineer (AMD)
Physical Design
Synthesis Place & Route STA Timing Closure Tcl
Staff Engineer, Design Verification Engineering (Analog Devices)
Verification
SystemVerilog UVM SoC Verification AI/ML SoC
Senior Analog Layout Design Engineer (SiMaxTech)
Analog Layout
Analog Layout Custom Layout Virtuoso DRC/LVS
Physical Design Engineer (EdgeSilica)
Physical Design
Physical Design Floorplanning CTS STA Signoff
Design Verification Engineer — SoC (Oceancore Technologies)
Verification
SystemVerilog UVM SoC Verification Regressions
HW and DSP Graduate Intern — Wireless 5G/6G IP (Altera)
✅ Fresher FriendlyFPGA
Verilog DSP Wireless Algorithms FPGA 5G/6G
Summer 2027 Intern — Hardware Engineering (WD)
✅ Fresher FriendlyRTL Design
Digital Design Verification Simulation SystemVerilog
India Campus Hiring — ASIC/SoC Design, Verification, Physical Design (Micron)
✅ Fresher FriendlySoC Architecture
ASIC Design Design Verification Physical Design Digital Design
Infra Design Verification Sr Lead Engineer (Qualcomm)
Verification
SystemVerilog UVM PCIe SoC Verification
Senior Design Verification Engineer — RISC-V & DDR (Tessolve)
Verification
SystemVerilog UVM RISC-V DDR Verification
Principal Verification Engineer (Microchip Technology)
Verification
SystemVerilog UVM SoC Verification Debugging
DFT ASIC Engineering Technical Leader — ATPG (Cisco)
DFT
DFT ATPG Scan MBIST
RTL Design Lead (MediaTek)
RTL Design
RTL Design Verilog/SystemVerilog SoC Architecture Team Leadership
Design For Testability Engineer (Tattvasemi Technologies)
DFT
DFT Scan Insertion ATPG ASIC/SoC Test
IC Verification Engineer (Broadcom)
Verification
SystemVerilog UVM/VMM Object-Oriented Programming
Senior STA Engineer (Samsung Semiconductor)
Physical Design
Static Timing Analysis PrimeTime Timing Closure
ASIC Engineer Intern, Design (Meta)
✅ Fresher FriendlyRTL Design
Verilog/SystemVerilog RTL Design Verification Python
Sr Engineer Tapeout Engineering (GlobalFoundries)
✅ Fresher FriendlyPhysical Design
Tapeout GDS Physical Verification Semiconductor Manufacturing
Analog Design Engineer (circuitEvolve)
✅ Fresher FriendlyAnalog/Mixed-Signal
Analog Circuit Design Cadence Simulation
Senior Principal Engineer — Digital Design (Renesas)
RTL Design
Digital ASIC/SoC Design RTL Verilog
Physical Design Engineer (Ample Semiconductors)
Physical Design
Floorplanning Placement CTS Routing Timing Closure DRC
Lead Design Verification DDR Engineer (Cadence)
Verification
SystemVerilog UVM DDR Functional Verification
Design Verification Engineer (SmartSoC Solutions)
Verification
SystemVerilog UVM SoC Verification
Principal Verification Engineer (NXP Semiconductors)
Verification
IP/Subsystem Verification SystemVerilog UVM
ASIC Design Engineer — New College Grad 2027 (NVIDIA)
✅ Fresher FriendlyRTL Design
RTL Design Verilog ASIC Flow Verification
Early Career — GPU Physical Design Engineer (Apple)
✅ Fresher FriendlyPhysical Design
Physical Design Place & Route Floorplanning Timing Signoff
Hardware Engineering Intern, PhD, Summer 2027 (Google)
✅ Fresher FriendlyAI Silicon
Hardware Design Silicon Digital Design
Senior Design Verification Engineer (eInfochips)
Verification
SystemVerilog UVM SoC Verification
VLSI High-Speed Design Engineer (HCLTech)
SoC Architecture
DDR LPDDR5 SerDes HBM Design & Verification
Physical Design Engineers (Kandou AI)
Physical Design
Physical Design Advanced Process Nodes Floorplanning STA Signoff
Staff Engineer — Verification / Silicon Validation (Infineon)
Verification
FPGA Silicon Validation Characterization Test Automation Python
Senior Verification Engineer — IP/SoC (LeadSOC Technologies)
Verification
SystemVerilog UVM IP/SoC Verification Sub-system DV
Analog Layout Engineer (leadIC Design)
Analog Design
Analog Layout Mixed-Signal Cadence Virtuoso DRC/LVS
Firmware / Bare-metal / Low-level Drivers Lead-Architect (Mirafra Technologies)
SoC Architecture
Embedded C Bare-metal Low-level Drivers SoC Firmware
Emulation Engineering Intern (Astera Labs)
✅ Fresher FriendlyVerification
Emulation ASIC Pre-Silicon Validation Verilog/SystemVerilog Scripting
ASIC Design Engineer Intern — Video Silicon IP, 2027 Summer (ByteDance)
✅ Fresher FriendlyRTL Design
RTL Design Verilog/SystemVerilog Video Codec IP ASIC Flow
VLSI Trained Fresher — SoC Verification (Vaaluka Solutions)
✅ Fresher FriendlyVerification
SoC Verification SystemVerilog UVM PCIe Verilog
Lead Analog Design Engineer (Texas Instruments India)
Analog Design
Analog IC Design Mixed-Signal Cadence Virtuoso Circuit Simulation
Research Intern (PhD) — FPGA & Silicon Prototyping (Marvell)
✅ Fresher FriendlyFPGA
FPGA Silicon Prototyping RTL Verilog Python
Senior Engineer, Low Power CLP (Arm)
Physical Design
Low Power CLP Logical Signoff Structural Verification
Engineer — Hardware Design (Qualcomm)
RTL Design
Hardware Design Digital Design System Design
Verification Engineer, Media IP (Arm)
Verification
Constrained-Random Verification SystemVerilog UVM Media IP
Design Verification Engineer / Senior Member Technical Staff (Core ASIC)
Verification
SystemVerilog UVM Functional Verification Debug
Synthesis CAD Engineer (AMD)
EDA Tools
CAD Flow Development Synthesis Methodology Scripting
2027 Campus Hire Engineer, Hardware (Qualcomm)
✅ Fresher FriendlySoC Architecture
Digital Design Verilog Computer Architecture Modem/Multimedia HW
R&D Engineer, IP Quality (Synopsys)
✅ Fresher FriendlyEDA Tools
IP Validation Testing Quality Assurance Scripting
VLSI Engineer — Fresher (Wipro)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog Digital Design
Physical Design Engineer (Syntiant)
Physical Design
RTL to GDSII Physical Design Place and Route STA
SoC Physical Design Engineer — Lead/Staff/Senior Staff (Qualcomm)
Physical Design
Physical Design Floorplanning CTS Timing Closure
Formal Verification Engineer (Intel)
Verification
Formal Verification SystemVerilog Assertions JasperGold RTL
Senior Physical Design Engineer (MosChip)
Physical Design
Physical Design Floorplan CTS STA PnR
Design Verification Technical Leader (STMicroelectronics)
Verification
Digital Design IP Verification SystemVerilog UVM
SMTS - CPU Design Verification Engineer (GlobalFoundries)
Verification
CPU Verification SystemVerilog UVM Computer Architecture
Principal Engineer, ASIC Design Verification (Ayar Labs)
Photonics
ASIC Verification Silicon Photonics SystemVerilog UVM
Intern - ASIC Validation (Micron Technology)
✅ Fresher FriendlyVerification
ASIC Validation Silicon Characterization Python Digital Design
New College Grad - HBM PSE Design Validation (Micron Technology)
✅ Fresher FriendlyAI Silicon
HBM JEDEC Silicon Validation Memory Design Python
Sr/Staff Engineer, Design Verification - System IP (Tenstorrent)
Verification
SystemVerilog UVM System IP Verification SoC
Senior Design Verification Engineer (Analog Devices)
Verification
SystemVerilog UVM SoC Verification Automotive Connectivity
FPGA Verification Intern (Eon Space Labs)
✅ Fresher FriendlyFPGA
FPGA Verilog/SystemVerilog Verification Testbench RTL Debug
Principal Engineer, System HW Design — SI/PI (SiMa.ai)
Packaging
Signal Integrity Power Integrity High-Speed Design Packaging PCB
Silicon Power Architect, Reality Labs (Meta)
SoC Architecture
Silicon Power Architecture SoC Power Management C/C++ Python
Principal ADC Engineer (Omni Design Technologies)
Analog/Mixed-Signal
ADC Design Analog/Mixed-Signal IC Advanced CMOS Cadence Virtuoso
ASIC Principal Engineer (Hewlett Packard Enterprise)
RTL Design
ASIC Design RTL VLSI Architecture Technical Leadership
Design Verification Engineer (QTIMINDS)
Verification
SystemVerilog UVM Design Verification Functional Coverage
Applied Machine Learning Engineer, AI for VLSI Design — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyAI Silicon
Machine Learning Python Circuit Design VLSI EDA
ASIC Verification Engineer, Memory Management — New College Grad 2027 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM ASIC Verification Memory Management Python
ASIC Floorplan Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Floorplanning Physical Design Tcl Python ASIC Implementation
EDA Simulation Automation Engineer (onsemi)
EDA Tools
TCAD Power Semiconductor Simulation Python Automation EDA
RTL Design Engineer — SoC (Cyient)
RTL Design
RTL Coding SoC Design ASIC Flow Verilog SystemVerilog
SoC Architect — ARM Cortex Systems & Product Definition (Texas Instruments)
SoC Architecture
SoC Architecture ARM Cortex Digital Design System Architecture
Physical Design Lead — Full Chip (7Rays Semiconductors)
Physical Design
Full-Chip Physical Design Floorplanning CTS STA Signoff
CPU Verification Engineer (Ambit Semiconductors)
Verification
CPU Verification SystemVerilog UVM Processor Architecture Assembly
Analog Layout Engineer (ARF Design)
Analog Layout
Analog/Mixed-Signal Layout FinFET 3-7nm DRC/LVS Cadence Virtuoso
Lead Engineer — Physical Design (Siliconus Technologies)
Physical Design
Physical Design Timing Closure Signoff Block/Full-Chip PnR
Functional System Validation Engineer (UST)
✅ Fresher FriendlyVerification
SoC Validation Digital/Mixed-Signal Driver Development Python C
New College Grad — HBM Digital Verification Engineer (Micron, Mexico)
✅ Fresher FriendlyVerification
SystemVerilog UVM Testbench Development HBM/DRAM Debug
Physical Design Engineer, Lead (Qualcomm)
Physical Design
RTL-to-GDS Floorplanning CTS Timing Closure ASIC Design
Silicon Engineer, Platform and Devices — University Graduate 2026 (Google)
✅ Fresher FriendlyRTL Design
Digital Design Verilog/SystemVerilog Computer Architecture Python
RTL Design Engineer (AMD)
✅ Fresher FriendlyRTL Design
RTL SystemVerilog ASIC/FPGA Design Verification Scripting
FPGA and ASIC Design Engineer — Spanidea
FPGA
FPGA ASIC Verilog SystemVerilog RTL
CPU Design Engineer — Scaledge Technology
SoC Architecture
CPU Microarchitecture RTL RISC-V SystemVerilog
Principal Physical Design Engineer — NXP Semiconductors
Physical Design
Digital Physical Design RTL-to-GDSII STA Floorplanning
Senior FPGA Engineer — Data Patterns
FPGA
VHDL Verilog FPGA Architecture RTL Design
RTL Design Engineer (Verilog/ASIC) — Sykatiya Technologies
RTL Design
Verilog SystemVerilog Synthesis Timing Analysis
DFT Engineer — leadIC Design
DFT
Scan Insertion ATPG Test Compression BIST MBIST
Digital Verification Apprenticeship (Fresher) — Synopsys
✅ Fresher FriendlyVerification
SystemVerilog UVM Digital Design Verification
Software Engineer Associate — Siemens EDA (Fresh Graduates)
✅ Fresher FriendlyEDA Tools
Verilog SystemVerilog ASIC Design Flow Digital Logic Synthesis
Assistant Engineer — Infineon Technologies (Fresher)
✅ Fresher FriendlySoC Architecture
Microcontrollers SoC Digital Design Embedded
Senior/Lead Physical Design Engineer — Zerlon Semi
Physical Design
Floorplanning Placement CTS STA Innovus/ICC2
Principal Engineer, Design Verification Engineering (Analog Devices)
Verification
SystemVerilog UVM Mixed-Signal Verification Python
Senior Engineer II — FPGA Verification Engineer (Microchip Technology)
FPGA
FPGA Verification SystemVerilog UVM Python
Principal Engineer, ASIC Design Verification — Silicon Photonics (Ayar Labs)
Photonics
ASIC Verification UVM Silicon Photonics Mixed-Signal
Senior Physical Design Engineer — AI Chip (EnCharge AI)
Physical Design
Physical Design RTL-to-GDSII Innovus/ICC2 STA
Lead RTL Engineer — Mixed-Signal IPs (Silicon Labs)
RTL Design
RTL Design Verilog Mixed-Signal Integration Verification
2027 Campus Hire — Associate Engineer, Hardware (Qualcomm)
✅ Fresher FriendlySoC Architecture
Digital Design Verilog Computer Architecture Modem/Multimedia HW
Analog Design Intern — BS, 2027 Co-Op (Marvell)
✅ Fresher FriendlyAI Silicon
Analog Design Cadence Virtuoso Op-Amps SerDes/PLL
Analog Layout Intern, BS — Summer 2027 (Marvell)
✅ Fresher FriendlyPhysical Design
Analog Layout Cadence Virtuoso DRC/LVS Calibre
Silicon Engineering Intern, BS/MS — Summer 2027 (Google)
✅ Fresher FriendlyAI Silicon
Verilog/SystemVerilog Computer Architecture ASIC Flow Python
Digital Design & RTL Engineer — High-Speed Automotive SerDes SoCs (Texas Instruments)
RTL Design
RTL Design SystemVerilog SerDes Low Power Synthesis
ASIC Physical Design Engineer — Sovereign SLM Labs
Physical Design
Floorplanning P&R Timing Closure Extraction
SoC Front-End Design & Signoff Engineer — Amlogic
SoC Architecture
RTL Lint CDC Synthesis Networking SoC
Senior Principal Digital Design Engineer — PCIe/CXL — Kandou AI
AI Silicon
PCIe CXL Digital Design RTL AI Interconnect
VLSI Engineer L2 — Wipro
RTL Design
VLSI RTL Verification Physical Design
Senior RTL Design Engineer — Tessolve
RTL Design
RTL Design Verilog SystemVerilog Lint CDC
Senior ASIC RTL Design Engineer — SmartSoC Solutions
RTL Design
ASIC RTL Microarchitecture SoC Integration SystemVerilog
Silicon Engineering Intern — Microsoft
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog Digital Design Computer Architecture
Hardware Design Engineer (Intern) — Bytebeam
✅ Fresher FriendlyFPGA
Digital Design Verilog FPGA PCB Embedded
Silicon Design Engineer 1 — AMD
RTL Design
RTL Design Verilog SystemVerilog Scripting
Design Engineer I (Synthesis/LEC/CLP) — Cadence
✅ Fresher FriendlyEDA Tools
Synthesis LEC Conformal Low Power Verilog TCL
FPGA Prototyping & Bring-Up Engineer (RTLYNX Semicon)
FPGA
FPGA Prototyping Bring-Up Camera Serializer IP Digital Subsystems
Junior Field Applications Engineer, ASIC Design (Synopsys)
EDA Tools
ASIC Design EDA Tools Application Engineering
Lead Design Verification Engineer (BITSILICA)
Verification
SystemVerilog UVM IP/Subsystem/SoC Verification
SoC Physical Design Engineer, Top Level (Apple)
Physical Design
Netlist to Tapeout Physical Design Chip Implementation
R&D Engineering, Sr Engineer — Circuit Design (Synopsys)
✅ Fresher FriendlySoC Architecture
Circuit Design VLSI Engineering Memory Design
Memory Circuit Design Engineer (Micron Technology)
✅ Fresher FriendlyAnalog/Mixed-Signal Design
DDR5 LPDDR5 LPDDR6 HBM3 Memory Circuit Design
Semiconductor Package Electrical Engineer (Micron Technology)
Packaging
Package Electrical Modeling Signal Integrity Test Plan Validation
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog RTL Design Synthesis Timing Analysis ASIC Design Flow
Senior ASIC Design Verification Engineer — LPU (NVIDIA)
Verification
SystemVerilog UVM Sign-off Verification Inference Accelerators
Analog Circuit Design Engineer (Intel)
Analog/Mixed-Signal Design
Analog Design Mixed-Signal Circuits High-Speed Chip-to-Chip Interfaces
Staff Engineer, Validation (Renesas Electronics)
Post-Silicon Validation
Silicon Validation Mentoring Bring-up Debug
Design Verification Engineer (Digicomm Semiconductor)
Verification
SystemVerilog UVM Functional Verification
Engineer — Memory Design (Fresher/Early Career) (Arm)
✅ Fresher FriendlySoC Architecture
Memory Design Characterization Circuit Design
System Validation Engineer — New Grads (SiFive)
✅ Fresher FriendlyVerification
RISC-V System Validation Post-Silicon Bring-up Python
Digital Design - PD Engineer — TMG New College Graduate Program (Texas Instruments India)
✅ Fresher FriendlyRTL Design
Digital Circuit Design Verilog RTL Digital Modeling
Memory Layout Design Engineer (Broadcom)
Physical Design
Cadence Virtuoso Layout XL Memory Layout Custom Layout
Silicon Engineer, Custom Circuits and SRAM — Google Cloud (Google)
AI Silicon
Custom Circuit Design SRAM Analog/Mixed-Signal Silicon Architecture
Principal Design Engineer (RTL) — NXP Semiconductors
RTL Design
RTL Design Verilog IP Delivery Silicon Validation ASIC Design Cycle
Sr Engineer Design — SoC DFT Engineer (GlobalFoundries)
DFT
DFT SoC Design Custom Silicon ATPG Scan
High Speed IP Validation Engineer — NXP Program (Tessolve)
Post-Silicon Validation
Post-Silicon Validation High-Speed IP Characterization Debug
ASIC/SoC Verification Engineer (HCLTech)
Verification
ASIC Verification SoC SystemVerilog UVM
Senior STA Engineer (Qualcomm)
Physical Design
Static Timing Analysis ASIC Design Validation Integration
Senior DFT Engineer (onsemi)
DFT
DFT ATPG Scan Insertion Design-for-Test
Senior Design Engineer — Post Silicon Validation (Lattice Semiconductor)
Silicon Validation
Post-Silicon Validation FPGA Bring-up Lab Debug
Staff, VLSI Design Engineering — Verification (Sandisk)
Verification
UVM SystemVerilog Formal Verification Memory Design
Design Verification Engineer (AMD)
Verification
SystemVerilog UVM RTL Design Software Development
Junior Engineer — Physical Design VLSI (Route2SOC Technologies)
✅ Fresher FriendlyPhysical Design
Physical Design Floorplanning Place & Route STA
Intern — IC Design (Silicon Labs)
✅ Fresher FriendlyIC Design
Analog/Mixed-Signal IC Design Circuit Design Verilog
IP RTL Design Engineer (Samsung Semiconductor)
RTL Design
RTL Design Verilog SystemVerilog IP Design Microarchitecture
Graduate Engineer, SoC PnP Architect (Arm)
✅ Fresher FriendlySoC Architecture
SoC Architecture Verification Digital Design ARM Architecture
Analog/Mixed-Signal IC Design Engineer — New College Graduate Hire (Omni Design Technologies)
✅ Fresher FriendlyRTL Design
Analog IC Design Mixed-Signal Circuits ADC/DAC Cadence
Staff Engineer, Design Verification Engineering (Analog Devices)
Verification
SystemVerilog UVM Digital Design Verification Formal Verification
FPGA Silicon Design Engineer (Altera)
FPGA
FPGA Custom IC Design ASIC Verification Logic Design
Silicon Photonics Switch Architect (Qpisemi)
Photonics
Silicon Photonics Optical Switching PIC Design Co-Packaged Optics
IO/Analog Layout Engineer (STMicroelectronics)
Physical Design
Layout Design Analog IC IO Cells Cadence Virtuoso
Digital Design Engineer — AI Accelerators (STMicroelectronics)
AI Silicon
RTL Design Verilog AI Accelerator Architecture SystemVerilog
DFT Engineer (MediaTek)
DFT
DFT ATPG STA Logic Equivalence Check
Physical Design and Timing Engineer Intern — Summer 2027 (NVIDIA)
✅ Fresher FriendlyPhysical Design
RTL to GDSII Physical Design EDA Tools Python STA
SoC Power Validation Engineer (Apple)
SoC Architecture
Power Validation SoC Hardware Python C Lab Bring-up
Product Design Engineering Intern — iPhone (Apple)
✅ Fresher FriendlySoC Architecture
Hardware Design CAD Product Development DFM
ASIC RTL Design Engineer (Sauvira Solutions)
RTL Design
RTL Design Verilog SystemVerilog ASIC Design Flow
Sr. Staff Engineer, Design Verification (SiFive)
Verification
ASIC/SoC/IP Verification UVM SystemVerilog RISC-V
Senior Silicon Engineer, DFT (Microsoft)
DFT
DFT Scan ATPG Silicon Design for Test
ASIC Engineer — Physical Design | Floor Planning | GSP & PD (Cisco)
✅ Fresher FriendlyPhysical Design
Floorplanning Place & Route GSP Physical Design
Applications Engineer — ICV Runset Development (Synopsys)
Physical Design
ICV Physical Verification DRC/LVS EDA Tools
PDK Engineer (Intel)
EDA Tools
PDK Development VLSI Electronics Process Design Kits
Design Engineer II — PDK Enablement (Cadence)
EDA Tools
Semiconductor Technology Analysis Foundry PDK Co-optimization
Young Graduate Trainee — Silicon Validation (Infineon Technologies)
✅ Fresher FriendlyVerification
Python LabVIEW FPGA Post-Silicon Validation Microcontrollers
Hardware Engineer Intern — Campus Hiring, Nirma 2026/27 (Arista Networks)
✅ Fresher FriendlySoC Architecture
Digital Design Hardware Bring-up Networking Hardware Verilog
Technician Apprentice — Semiconductor Fab (Micron Technology)
✅ Fresher FriendlyPackaging
Wiring & Harness Fab Operations Equipment Handling
Silicon Engineer, Platform and Devices — University Graduate 2026 (Google)
✅ Fresher FriendlyAI Silicon
SoC Architecture Silicon Bring-up Digital Design Verilog
VLSI Engineer L3 (Wipro)
RTL Design
VLSI Design RTL Synthesis Verification
Physical Design Engineer — Fresher/Early Career (EdgeSilica)
✅ Fresher FriendlyPhysical Design
Floorplanning Placement CMOS RTL to GDSII
Associate VLSI Design Engineer — Fresher (Electro Global)
✅ Fresher FriendlyRTL Design
VLSI Fundamentals Verilog Digital Design
Emulation Engineer (Tessolve)
EDA Tools
Emulation Synopsys Zebu Pre-Silicon Validation
Lead DFT Engineer — MBIST (GlobalFoundries)
DFT
DFT MBIST ATPG Scan JTAG
Physical Verification Engineer (Digicomm Semiconductor)
Physical Design
Physical Verification DRC LVS Calibre
Memory Design Engineer (Broadcom)
SoC Architecture
SRAM Memory Compilers Circuit Design Custom Layout
RTL Engineer — Analog & Mixed-Signal (Texas Instruments India)
RTL Design
RTL Design Verilog Mixed-Signal CMOS Digital Design
Senior Staff Engineer, Design Verification — Power & Analog ICs (Renesas Electronics)
Verification
SystemVerilog UVM Mixed-Signal Verification DFT Post-layout Verification
Intern — Micron Technology
✅ Fresher FriendlyAI Silicon
Semiconductor Design Data Science Engineering Fundamentals
Intern — Hardware (Silicon Labs)
✅ Fresher FriendlySoC Architecture
Digital Design Circuit Fundamentals Verilog Lab Bring-up
Sr. IP/CPU RTL Design Lead — CPU Team (AMD)
RTL Design
RTL Design CPU Microarchitecture Verilog VLSI Design
AMS Verification Engineer — Digicomm Semiconductor
Verification
AMS Verification SPICE SystemVerilog Mixed-Signal Simulation
Design Verification Engineer — Entry Level (EdgeSilica)
✅ Fresher FriendlyVerification
SystemVerilog UVM Testbench Development Digital Design Fundamentals
Senior Staff VLSI Design Engineer — Sandisk
RTL Design
VLSI Design SystemC C++ Functional Modeling Verification
DFT Engineer — Arm
DFT
DFT Scan Insertion ATPG Verilog TCL/Perl
Staff Digital Design Engineer — NXP Semiconductors
RTL Design
RTL Design Verilog MCU Architecture Embedded Processing
Analog Circuit Engineer — HCLTech
Analog/Mixed-Signal
Analog Circuit Design CMOS Deep Sub-micron Cadence Virtuoso
GPU Physical Design Engineer (Senior/Lead) — Qualcomm
Physical Design
Physical Design ICC2/Innovus STA Floorplanning GPU Architecture
Silicon Validation Engineer 1 (Tessolve)
✅ Fresher FriendlyVerification
Silicon Validation ATE Characterization Bench Testing
Design For Test Engineer (EdgeSilica Private Limited)
DFT
DFT Scan Insertion ATPG BIST
Principal Physical Design Engineer (NXP Semiconductors)
Physical Design
Physical Design ICC2 Innovus STA Floorplanning
STA & Custom Logic Design Engineer (Apple)
Physical Design
Static Timing Analysis PrimeTime Tempus NanoTime Custom Logic
AMS CAD Lead (Tata Electronics)
EDA Tools
Analog Mixed-Signal CAD Flows Circuit Design EDA Tools
New College Grad — Design Readiness Engineer (Micron Technology)
✅ Fresher FriendlyAI Silicon
DRAM Design Validation Design Readiness Process Engineering
SOC Systems Software Engineer (Apple)
SoC Architecture
System Software SoC Test C/C++ Embedded Systems
Senior ASIC Hardware Design Engineer (NVIDIA)
RTL Design
RTL Verilog Chip Architecture Verification Timing Closure
Senior SOC Clocks RTL Design Engineer (NVIDIA)
SoC Architecture
PLL Clock Distribution RTL SoC Architecture
ASIC Design Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM RTL Verification Python
EDA Tools Hardware Engineer (Intel)
EDA Tools
SKILL Python TCL/PERL CAD Software Development
Lead Silicon Design Engineer (AMD)
SoC Architecture
Silicon Design DFT Verification Physical Design
SoC Audio Engineer, Platform Architecture (Apple)
SoC Architecture
Audio DSP Architecture Specification SoC Design
DFT Design Engineer (Intel)
DFT
Spyglass DFT Scan Architecture Fault Models
Staff DFT Engineer (AMD)
DFT
DFT Scan ATPG BIST
ASIC Design Engineer, Clocks (NVIDIA)
RTL Design
Clock Design PLL RTL Digital Design
ASIC Physical Design Engineer (NVIDIA)
Physical Design
Synthesis Place & Route STA Physical Design Signoff
Silicon Co-design Intern — 2027 (NVIDIA)
✅ Fresher FriendlyAI Silicon
GPU/SOC Bring-up Characterization Validation Python
VLSI Physical Design CAD Intern — Summer 2027 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Floorplan Power/Clock Distribution Placement Routing Timing Analysis
2026 Campus Hire — Associate Engineer, Hardware (Qualcomm)
✅ Fresher FriendlyRTL Design
Digital Design Verilog VLSI Fundamentals Hardware
Physical Design Application Engineer (Cadence)
EDA Tools
Innovus Physical Design PnR Customer Support EDA Tools
VLSI High-Speed Design Engineer (HCLTech)
RTL Design
DDR LPDDR SerDes HBM High-Speed Interface Design
Associate III — VLSI SD Char (UST)
Physical Design
Standard Cell Characterization Liberty Modeling VLSI
Physical Design Engineer — Fresher (Global Semicon Services)
✅ Fresher FriendlyPhysical Design
RTL Concepts Verilog VHDL Physical Design Basics
2027 Undergrad Hardware Engineering Intern/Co-Op (AMD)
✅ Fresher FriendlyRTL Design
ASIC Design Verification Digital Logic Verilog
Summer 2027 Long Term ASIC Verification Engineering Intern/Co-Op (AMD)
✅ Fresher FriendlyVerification
ASIC Verification SystemVerilog UVM Testbenches
Hardware System Engineer — iPhone System Technologies, SoC (Apple)
SoC Architecture
SoC Architecture System-Level Validation Electrical Engineering
Senior ASIC Design Engineer — Circuit Solutions (NVIDIA)
RTL Design
ASIC Design Circuit Design RTL Verilog Timing Analysis
Sr. Staff ASIC Design Engineer — Graphics & Compute (AMD)
AI Silicon
ASIC Design GPU Architecture RTL Physical Design Verilog
ASIC Design Engineer — Tools and Methodology Development (NVIDIA)
EDA Tools
ASIC Design RTL EDA Tools Scripting Design Methodology
Associate Engineer — Hardware (Qualcomm)
✅ Fresher FriendlySoC Architecture
Hardware Engineering Digital Design Computer Science Fundamentals
SoC Physical Design Engineer, PnR (Apple)
Physical Design
Physical Implementation PnR Timing Closure
SoC Logic Design Engineer (Intel)
RTL Design
RTL Design Logic Design SoC Architecture
VLSI Engineer L3 (Wipro)
SoC Architecture
VLSI System Design Architecture Layout Implementation
Principal Engineer, DFT (Qualcomm)
DFT
DFT Scan ATPG MBIST Hardware Engineering
Senior Staff SOC DFX Verification Engineer (AMD)
DFT
DFT Architecture Design-for-Test Verification SystemVerilog
Experienced SoC System Validation Engineer (Apple)
Verification
Pre-Silicon Validation Post-Silicon Validation SoC Development
ASIC Design Engineer — RTL and Circuits (NVIDIA)
RTL Design
Verilog Logic Design Circuit Design ASIC Flow
ASIC Physical Design Engineer — RDSS Intern (NVIDIA)
✅ Fresher FriendlyPhysical Design
IC Design Implementation Circuit Design EE Fundamentals
Senior ASIC Physical Design Engineer, Cache Coherent — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Verilog ASIC Design Flow RTL DFT ECO
VLSI Engineer L2 (Wipro)
RTL Design
VLSI Design RTL Digital Design System Functionality
CPU Floorplan Lead (Intel)
Physical Design
Floorplanning Physical Design VLSI Microelectronics EDA Tools
New College Grad — Semiconductor Verification Design Engineer, DRAM Products Group (Micron)
✅ Fresher FriendlyVerification
Verilog DRAM Design Verification Digital Logic
Principal CAD Engineer (Renesas Electronics)
EDA Tools
CAD Flow Development Digital Implementation EDA Tools Integration
Hardware System Engineer — iPhone System Technologies, SoC (Apple)
SoC Architecture
System-level Hardware SoC Integration Electrical Engineering
Sr. Staff Design Verification Engineer (AMD)
Verification
Design Verification Physical Design Implementation UVM
STA Silicon Design Engineer (AMD)
Physical Design
Static Timing Analysis DFT Timing Closure Signoff
ASIC Engineering Intern — Networking Chip Design, 2027 (NVIDIA)
✅ Fresher FriendlyAI Silicon
RTL Design RTL Verification Scripting Networking ASIC
Senior ASIC Engineer — Switch SoC (NVIDIA)
Verification
ASIC Verification RTL SystemVerilog Networking Silicon
ASIC Design and Verification Intern, SOC — 2027 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog SystemVerilog RTL Design Testbenches Assertions
Design Verification Engineer 2 — IP/SoC (Lattice Semiconductor)
Verification
UVM IP Verification SoC Verification SystemVerilog Coverage
SoC Architect (NXP Semiconductors)
SoC Architecture
SoC Architecture System Specification Platform Design Microarchitecture
SoC Logic Design Engineer (Intel)
RTL Design
RTL Design Logic Design SoC Integration Verilog/VHDL
ASIC Digital Design, Staff Engineer (Synopsys)
RTL Design
RTL Design Verilog Microarchitecture ASIC Design Flow
Associate Engineer — B.Tech 2026 (Qualcomm)
✅ Fresher FriendlySoC Architecture
Embedded Systems Hardware Engineering C/C++ Digital Design
DFT ATPG Design and Test Engineer (AMD)
DFT
DFT ATPG Scan Insertion Static Timing Analysis Netlist Analysis
SoC Power Validation Engineer (Apple)
SoC Architecture
Power Validation SoC Hardware Signal Integrity Lab Bench Testing
ASIC Floorplan Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Floorplanning ASIC Physical Design Verilog EDA Tools
Formal Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
Formal Verification SystemVerilog ASIC Verification Assertions
ASIC Physical Design Engineer — RDSS Intern (NVIDIA)
✅ Fresher FriendlyPhysical Design
IC Design Implementation Circuit Design Physical Design Flow
Applications Engineering, Staff Engineer — Physical Verification (Synopsys)
EDA Tools
Physical Verification EDA Tools DRC/LVS Customer Support
Engineer I — Digital IP Design & Verification (SiFive)
✅ Fresher FriendlyRTL Design
RTL Design Verification VLSI CPU/SoC IPs
Engineer II, Physical Design — Cores (SiFive)
✅ Fresher FriendlyPhysical Design
Physical Design ASIC Flows Scripting
Physical Design Engineer — Entry Level (Digicomm Semiconductor)
✅ Fresher FriendlyPhysical Design
Physical Design PnR STA Basics VLSI Fundamentals
Short Term 2027 Hardware Design Engineering Intern/Co-Op (AMD)
✅ Fresher FriendlyRTL Design
Verilog VHDL Digital Logic VLSI Design Flow
Staff Engineer — Design Enablement (Renesas Electronics)
EDA Tools
EDA VLSI Design Enablement PDK CAD Flows
Physical Design Intern (SEMIFIVE)
✅ Fresher FriendlyPhysical Design
Physical Design PnR VLSI Basics Scripting
Senior ASIC Verification Engineer — GPU (NVIDIA)
Verification
SystemVerilog UVM ASIC Verification GPU Architecture
SoC Physical Design Engineer, Staff — HM PD Team (Qualcomm)
Physical Design
Physical Design PnR STA Floorplanning
Physical Design Lead — High Speed IPs (AMD)
Physical Design
Physical Design High Speed IP PnR Timing Closure
Career Accelerator Program — Digital IC Design Engineer (Texas Instruments India)
✅ Fresher FriendlyRTL Design
Digital Circuit Design Verilog RTL Verification
Engineer, Digital Design — Graduate Engineer (Renesas Electronics)
✅ Fresher FriendlyRTL Design
Digital IP Design Verilog RTL Chip Verification
Engineer I — IC Design, 2026 Campus Hire (Silicon Labs)
✅ Fresher FriendlyRTL Design
IC Design Analog/Digital Circuits CMOS Verilog
Staff Application Engineer — Physical Implementation (Synopsys)
EDA Tools
Physical Implementation PPA Optimization Place and Route EDA Tools
SDC, Synthesis and STA Engineer (AMD)
Physical Design
SDC Synthesis Static Timing Analysis Design Constraints
SoC Pre-Silicon Engineering Program Manager (Apple)
SoC Architecture
SoC Architecture VLSI Chip Design ASIC Chip Design Program Management
DFT Engineer (AMD)
DFT
DFT ATPG Scan Insertion JTAG Boundary Scan
Senior Digital Design Engineer (NVIDIA)
RTL Design
RTL Design Verilog SystemVerilog Digital Logic ASIC
Senior ASIC Timing Engineer (NVIDIA)
Physical Design
Static Timing Analysis PrimeTime Synthesis Physical Design
GPU AI Performance Engineer (Qualcomm)
AI Silicon
GPU Architecture AI Workloads Performance Optimization CUDA/OpenCL
Engineer, STPG PE (Micron Technology)
SoC Architecture
NAND SSD Electrical Engineering Product Engineering
SoC Audio Engineer, Platform Architecture (Apple)
SoC Architecture
SoC Architecture Audio Processing System Design
SoC DRAM Memory Subsystem Validation Engineering Program Manager (Apple)
SoC Architecture
DRAM Validation Program Management SoC Memory Subsystem
Senior PDE, Test and Product Engineering, Client APU (AMD)
DFT
DFT Product Engineering Design Platform Validation Manufacturing
Senior ASIC Design Verification Infrastructure and Tools Engineer — GPU (NVIDIA)
Verification
RTL Compose Pre-silicon Verification CI/CD Automation Python
ASIC Engineer — RTL Design-Quality Methodologies (NVIDIA)
RTL Design
RTL Design Design Quality Methodologies Verilog Scripting
SoC Physical Design Engineer, Staff — HM PD Team (Qualcomm)
Physical Design
Physical Design Place and Route STA Circuit Optimization
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog ASIC Design Flow RTL Design Logic Synthesis DFT
ASIC Physical Design Intern — 2027 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Synthesis Formal Verification Constraints Physical Design
Associate Engineer — Hardware (Qualcomm)
✅ Fresher FriendlySoC Architecture
Hardware Engineering Digital Design Computer Science Fundamentals
Senior Lead Engineer — GPU Verification (Qualcomm)
Verification
GPU Verification Hardware Verification Circuit Bring-up Electronic Systems Test
Principal DFT Engineer (NXP Semiconductors)
DFT
DFT Scan Insertion ATPG Boundary Scan Design-for-Test Architecture
ASIC DFT Engineer (Cisco)
DFT
DFT Scan Chains ATPG ASIC Verification
Senior Principal Engineer — DFT (onsemi)
DFT
Design-for-Test DFx Architecture Scan/ATPG Silicon Bring-up
IP Verification Engineer (AMD)
Verification
UVM SystemVerilog IP Verification Digital Design
SoC QoS/Fabric Performance Engineer, Platform Architecture (Apple)
SoC Architecture
On-chip Interconnect Memory QoS SoC Architecture Performance Modeling
Physical Design PnR Tile Lead (AMD)
Physical Design
Place and Route Physical Implementation SoC Design Advanced Process Nodes
ASIC Physical Design and Timing Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Static Timing Analysis Place and Route Physical Design Synthesis
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog RTL Design Logic Synthesis DFT Timing Analysis
Cell Modeling and Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SPICE Circuit Simulation VLSI Cell Characterization
Packaging Integration Engineer — 2026 New College Graduate (GlobalFoundries)
✅ Fresher FriendlyPackaging
Packaging Advanced Packaging Semiconductor Assembly Process Integration
Physical Design Engineer — Fresher (Global Semicon Services)
✅ Fresher FriendlyPhysical Design
Physical Design Place and Route STA Floorplanning
New College Grad — Product Test Engineer (Micron Technology)
✅ Fresher FriendlyDFT
Test Program Development DRAM Debug ATE
Young Graduate Trainee (Infineon Technologies)
✅ Fresher FriendlySoC Architecture
Analog/Digital Electronics Microcontrollers SoC Basics
Staff Engineer — SOC Design Verification (Qualcomm)
Verification
SystemVerilog UVM SoC Verification Digital Design
Power Integrity Engineer — SoC Hardware (Apple)
SoC Architecture
Power Integrity SoC Hardware Technology Signal Integrity
Lead RTL Design & Validation Engineer — DDR Protocols (AMD)
RTL Design
RTL Design DDR Protocols Verilog Memory Controllers
Physical Design Engineer (Qualcomm)
Physical Design
Physical Design STA Place and Route SoC/ASIC
ASIC Design Engineer — Hardware (NVIDIA)
RTL Design
RTL Design Verilog Microarchitecture ASIC Design Flow
Senior ASIC Design Engineer — Agentic AI (NVIDIA)
AI Silicon
RTL Design Digital Design VLSI ASIC Design Flow Agentic AI
FPGA Verification Engineer (Skyroot Aerospace)
FPGA
RTL Verification FPGA SoC Integration VHDL/Verilog
ASIC Verification Engineer (Hewlett Packard Enterprise)
Verification
VLSI ASIC Verification RTL Scripting
Custom CPU Physical Design Engineer, Lead/Staff/Sr Staff (Qualcomm)
Physical Design
Physical Design CPU Custom Layout STA Innovus
Lead Physical Design Engineer (NXP Semiconductors)
Physical Design
Physical Design Innovus PrimeTime Floorplanning
Senior ASIC Verification Engineer — Coherent High Speed Interconnects (NVIDIA)
Verification
UVM Coherent Interconnects ASIC Verification C++
Senior Staff SOC DFX RTL Design Engineer (AMD)
DFT
DFT RTL Design Scan ATPG JTAG
Debug Tools SoC Design Engineer (Apple)
SoC Architecture
Silicon Debug SoC Validation Python JTAG
Verification Engineer — Mobile SoC Memory Subsystem, New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM Memory Subsystem ASIC Verification
New College Grad — FAB Process Engineer (Micron Technology)
✅ Fresher FriendlySoC Architecture
Semiconductor Fabrication Process Engineering Statistical Analysis
FPGA Design Verification Engineer — Intern (Altera)
✅ Fresher FriendlyFPGA
SystemVerilog FPGA Verification VLSI Fundamentals
FPGA Engineer Trainee (Celerix Technologies)
✅ Fresher FriendlyFPGA
FPGA Verilog RTL Coding Logic Design
DFT Engineer (NVIDIA)
✅ Fresher FriendlyDFT
DFT Static Timing Analysis ECO ASIC/Logic Design Flow HDL
SoC Hardware Architect (NXP Semiconductors)
SoC Architecture
SoC Architecture ISO26262 Multi-core Compute System Design
DFT Engineer III, Silicon (Google)
DFT
ASIC DFT Test Coverage SoC DFT Silicon Bring-up
High-Speed SERDES Validation Engineer (AMD)
Verification
SERDES Silicon Validation High-Speed IO Signal Integrity
2026 Campus Hire — Engineer, HW (Qualcomm)
✅ Fresher FriendlyRTL Design
VLSI RTL Design Embedded Digital Design
DFT Engineer, Custom Silicon (Qualcomm)
DFT
DFT Scan ATPG MBIST Custom Silicon
Senior ASIC Physical Design Engineer, Netlisting (NVIDIA)
Physical Design
Physical Design Netlisting Synthesis STA Timing Closure
Senior ASIC Physical Design Engineer, Cache Coherent Interconnect (NVIDIA)
Physical Design
Physical Design Synthesis Timing Power Cache Coherent Interconnect
CPU Verification Engineer — Core Enablement (AMD)
Verification
CPU Verification UVM SystemVerilog Core Architecture
PDE CEM Graduate Engineering Technician — Fab Operations (Micron Technology)
✅ Fresher FriendlyAI Silicon
Process Development Engineering Fab Equipment Data Analysis Yield Monitoring
Senior Physical Design Engineer (NXP Semiconductors)
Physical Design
Physical Design Place & Route Timing Closure Synthesis
HSIO Characterization Engineer (Qualcomm)
✅ Fresher FriendlyDFT
Post-Silicon Validation DDR High-Speed IO Characterization
Graduate Engineering Technician (Micron Technology)
✅ Fresher FriendlyPackaging
Semiconductor Fabrication Equipment Maintenance Process Monitoring
Senior Staff SOC DFX Verification Engineer (AMD)
Verification
SystemVerilog UVM DFT Design Verification SoC Debug
SoC Power Validation Engineer (Apple)
SoC Architecture
Power Grid Analysis IR Drop EM/IR Signoff Silicon Validation
Staff Memory Circuit Design Engineer (Broadcom)
Physical Design
Memory Design Circuit Design Custom Layout SRAM/CAM
Senior ASIC Design Engineer — XBAR IP (NVIDIA)
RTL Design
RTL Design Verilog SystemVerilog Synthesis Timing Closure
ASIC Engineer — CDC/RDC & Netlist Verification (NVIDIA)
Verification
CDC RDC Netlist Verification RTL Design Quality Formal Methodology
Senior Staff DFT Engineer (AMD)
DFT
DFT Scan Insertion ATPG MBIST Boundary Scan
Design Verification Engineer — VLSI (HCLTech)
Verification
SystemVerilog UVM Functional Coverage Formal Verification
Design Verification Engineer — Entry Level (EdgeSilica)
✅ Fresher FriendlyVerification
SystemVerilog UVM Digital Logic Verilog
Hardware System Engineer — iPhone System Technology, SoC (Apple)
✅ Fresher FriendlySoC Architecture
EE Fundamentals SoC Bring-up Circuit Analysis
System Integration Test Engineer — 5G-Advanced & Next-Gen 6G (Qualcomm)
SoC Architecture
5G 6G System Validation RF Test Protocol Stacks
AI/ML Silicon Verification Solutions Engineer — Tools (AMD)
AI Silicon
LLM Tooling AI Agents Verification Automation Python
Silicon Design Engineer — RTL Integration (AMD)
RTL Design
RTL Integration FPGA SoC Design Full-Chip RTL
SoC System Level Test Product Development Engineer (Apple)
SoC Architecture
System-Level Test Silicon Bring-up ATE Product Development
ASIC Design Engineer — RTL and Circuits (NVIDIA)
RTL Design
RTL Design Circuit Design Verilog SystemVerilog STA
ASIC Physical Design Engineer — RDSS Intern (NVIDIA)
✅ Fresher FriendlyPhysical Design
Synthesis Formal Verification Timing Closure RTL/Netlist QC
SOC Design Engineer — ASIC Tools and Methodology (NVIDIA)
EDA Tools
RTL Automation DevOps Python EDA Flows
Internship, AI Hardware Design Engineer — Fall 2026 (Tesla)
✅ Fresher FriendlyAI Silicon
AI Hardware ASIC Design Digital Design Python
DRAM Design Technology Layout Engineer (Micron Technology)
Physical Design
IC Layout DRAM Design Cadence Virtuoso Physical Verification
New College Graduate Systems Design Engineer (Renesas Electronics)
✅ Fresher FriendlyRTL Design
RTL Design Verilog Digital Design Microcontroller Architecture
Lead ASIC — FPGA Design Engineer (Boeing)
FPGA
FPGA VHDL ASIC Design Avionics Systems
Design Verification Engineer (AMD)
Verification
UVM SystemVerilog ASIC Verification GPU/CPU Verification
SoC Physical Design Engineer, Top Level (Apple)
Physical Design
Physical Design Floorplanning Timing Closure STA
Interim Engineering Intern — Systems 2026 (Qualcomm)
✅ Fresher FriendlySoC Architecture
Digital Design SoC Systems Verilog C/C++
Silicon Design Engineer — Core Debug (AMD)
✅ Fresher FriendlyRTL Design
RTL Design Verification Debug VLSI Fundamentals
GPU Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM ASIC Verification GPU Architecture
Senior ASIC Verification Engineer — HSIO (NVIDIA)
Verification
SystemVerilog UVM High Speed I/O Formal Verification
Intern — DRAM Design Engineer (Micron Technology)
✅ Fresher FriendlyAI Silicon
Analog Circuit Design Digital Design DRAM Memory Design
Associate Engineer (Micron Technology)
✅ Fresher FriendlySoC Architecture
VLSI Fundamentals Digital Electronics Verilog Problem Solving
Engineer I — IC Design (Silicon Labs)
✅ Fresher FriendlyAnalog IC Design
Analog IC Design Circuit Design Cadence Virtuoso Mixed-Signal
Associate II — Semiconductor Product Validation (UST)
✅ Fresher FriendlyVerification
Product Validation Test Automation Semiconductor Testing Debugging
DFX RTL Design Engineer (AMD)
DFT
DFT Scan Insertion ATPG RTL Design Verilog
Senior AI/ML — NPU Validation Engineer (AMD)
AI Silicon
NPU Validation Machine Learning Silicon Validation Python
SoC Physical Design Engineer, STA/Timing (Apple)
Physical Design
Static Timing Analysis Physical Implementation SoC Signoff
Senior ASIC Design Engineer — NOC IP (NVIDIA)
RTL Design
RTL Design Verilog SystemVerilog Network-on-Chip Microarchitecture
ASIC Design and STA Engineer (NVIDIA)
Physical Design
Static Timing Analysis PrimeTime Floorplanning Clock Domain Crossing
Physical Design Engineer (AMD)
Physical Design
Physical Design Place and Route Timing Closure ICC2/Innovus
Analog Design Engineer (Texas Instruments India)
Analog Design
Analog Circuit Design Mixed-Signal ICs Spice Simulation
RTL Design Engineer (HCLTech)
RTL Design
VHDL Verilog RTL Design Digital Design Methodologies
Senior VLSI Design Engineer — IO Design, High Speed DDR (Sandisk)
Physical Design
DDR5/LPDDR5 IO Design High-Speed Interface Design Circuit Design
Principal Analog IC Designer (Amber Semiconductor)
AI Silicon
Power Management ICs Power Conversion Topologies Control Theory Analog IC Design
Senior ASIC Design Verification Infrastructure and Tools Engineer — GPU (NVIDIA)
Verification
UVM SystemVerilog CI/CD Verification Infrastructure Python
SoC Power Validation Engineer (Apple)
SoC Architecture
Power Analysis SoC Validation Silicon Bring-up Lab Automation
Senior IC Packaging Engineer — 8 to 10 Years (MosChip)
Packaging
Semiconductor Packaging SoC/ASIC Package Design FPGA/HPC Package Development
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog RTL Design ASIC Flow Logic Synthesis Timing Analysis
Software Development Engineer — New College Grad Program (Texas Instruments India)
✅ Fresher FriendlyEDA Tools
C/C++ Embedded Software Digital Design Tools Python
Assoc Engineer — 2026 Campus Hire (Qualcomm)
✅ Fresher FriendlySoC Architecture
C/C++ Embedded Systems Digital Design Basics Debugging
SoC HW Systems Engineer — Packaging & IO (Infineon Technologies)
Packaging
Package Engineering Analog Design SoC System-Level Design
Senior Principal Engineer — Verification/AMS/SerDes (Marvell Technology)
Verification
AMS Verification SerDes SystemVerilog UVM
Sr Staff Engineer — Physical Design (Synopsys Inc)
Physical Design
Physical Design Synthesis STA Place & Route
SoC Silicon Validation Engineer (Samsung Semiconductor)
SoC Architecture
SoC Architecture Memory Hierarchy Embedded C ARM
Intern — Validation (Silicon Labs)
✅ Fresher FriendlyVerification
Silicon Validation Digital Design Debug Lab Testing
RTL Design Engineer (AMD)
RTL Design
RTL Design Verilog Microarchitecture ASIC Flow
Design Verification Engineer — DDR5/LPDDR5 (AMD)
Verification
SystemVerilog UVM DDR5 LPDDR5 Formal Verification Python
ASIC Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM RTL Verification Coverage
SOC Power Architecture Engineer (Qualcomm)
✅ Fresher FriendlySoC Architecture
SoC Power Architecture Hardware Engineering Low-Power Design
Verification Engineer — ARM Fabric Unit Level (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM ARM Fabric Formal Verification
Senior FPGA Design Engineer (Altera)
FPGA
FPGA Design Pre-Silicon Validation High-Speed Interfaces
AI/ML Driven ASIC Design and Implementation Automation Lead Engineer (NXP Semiconductors)
EDA Tools
AI/ML ASIC Design Automation EDA Scripting Python
FPGA Design Engineer (GE Vernova)
✅ Fresher FriendlyFPGA
FPGA Design VHDL/Verilog Embedded Software Basics
Hardware Intern (Micron Technology)
✅ Fresher FriendlySemiconductor Manufacturing
Digital Electronics Memory Basics Verilog Fundamentals
Associate Engineer — B.Tech 2026 (Qualcomm)
✅ Fresher FriendlySoC Architecture
Digital Electronics C/C++ Problem Solving Embedded Basics
Power & Performance Hardware Engineer, Platform Architecture (Apple)
SoC Architecture
SoC Power Analysis CPU/GPU Benchmarking Performance Modeling
Senior Staff VLSI Design Engineer — SystemC, Functional Modeling, C++, Verification (Sandisk)
Verification
SystemC C++ Functional Modeling Verification
Senior Design Verification Engineer (Excel VLSI Technologies)
Verification
SystemVerilog UVM ASIC/IP/SoC Verification
Senior ASIC Design Engineer — Agentic AI (NVIDIA)
AI Silicon
Verilog RTL Design Micro-architecture Agentic AI Silicon
ASIC Physical Design Engineer (NVIDIA)
Physical Design
Synthesis Formal Check Physical Design RTL to GDSII
Circuit Design Engineer — Library (Apple)
Physical Design
Standard Cell Design Circuit Design SPICE Library Characterization
Hardware Design Intern (Yorag Technologies)
✅ Fresher FriendlySoC Architecture
Hardware Design PCB Schematic Capture DfX NPD/NPI
Physical Design Engineer (AMD)
Physical Design
ASIC Physical Design Floorplanning Placement CTS Routing
STA Engineer (AMD)
Physical Design
Static Timing Analysis Physical Design ECO PrimeTime
Wireless Systems Test Engineer — WLAN & Edge AI (Qualcomm)
AI Silicon
WLAN System Testing Edge AI RF QA Automation
Engineer, Digital Design — IIT/NIT Graduates (Renesas Electronics)
✅ Fresher FriendlyRTL Design
RTL Verilog Digital Design Computer Architecture
Senior Lead Engineer — Physical Design (Qualcomm)
Physical Design
Physical Design Floorplanning Placement CTS Routing STA
RTL Power Optimization Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
RTL Verilog Power Analysis Low Power Design ASIC
CPU Floorplan Lead (Intel)
Physical Design
Floorplanning Physical Design VLSI Microelectronics
Principal Digital Engineer — DFT Design (Renesas Electronics)
DFT
DFT ATPG Scan Insertion RTL ASIC/SoC
Application Specific Integrated Circuit Engineer — Entry Level (Miryalan)
✅ Fresher FriendlyAI Silicon
ASIC Design Electronics Digital Design Basics
Senior Design Verification Engineer (Sauvira Solutions)
Verification
Verilog SystemVerilog UVM Verification
VLSI Post Silicon Validation Engineer — Entry Level (HCLTech)
✅ Fresher FriendlyVerification
Post Silicon Validation Digital & Mixed Signal Lab Equipment
Input Output Layout Engineer (Tessolve)
Physical Design
IO Layout Physical Design Custom Layout DRC/LVS
PDK Engineer (Intel)
EDA Tools
PDK Development VLSI Process Design Kit Layout
VLSI Engineer L3 (Wipro)
RTL Design
VLSI Design Architecture Layout Implementation
Silicon Photonics Switch Architect (Qpisemi)
Photonics
Silicon Photonics Optical Switching Photonic Integration Architecture
ASIC Design Engineer, High Speed IO (NVIDIA)
RTL Design
RTL Design Verilog High Speed IO UFS PCIe USB
Cell Modeling and Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
RTL Simulation Waveform Debug Verilog Cell Characterization
Silicon Power and Performance Engineer (Qualcomm)
SoC Architecture
ARMv9 CPU Performance Power Analysis Server SoC
Associate Engineer — IC Design (Silicon Labs)
✅ Fresher FriendlyRTL Design
Digital IC Design Verilog RTL Digital Electronics
Semiconductor PE Tech — Product Engineering Technician (Anora)
✅ Fresher FriendlyPhysical Design
Semiconductor Test Production Engineering ATE
Debug Tools SoC Design Engineer (Apple)
SoC Architecture
SoC Design Silicon Debug Validation Tools Architecture
Embedded Electronics & Hardware Prototyping Intern (Unio Labs)
✅ Fresher FriendlyFPGA
PCB Design Embedded Systems IoT Sensors FPGA Prototyping
Test Design Engineer — DFT & ATPG (EdgeSilica)
DFT
DFT ATPG EDA Tools Scan Insertion
Senior Principal Engineer — SPE Signal Integrity, Packaging (Rambus)
Packaging
Signal Integrity Package Design High-Speed Interfaces
Staff Engineer, VLSI Design Engineering — SOC Verification, UVM (Sandisk)
Verification
UVM SystemVerilog SoC Verification Coverage Closure
Design & Verification Engineer — IP/SoC Projects (AIonSi)
Verification
SystemVerilog UVM Verification ASIC IP Verification
Senior SOC Clocks RTL Design Engineer (NVIDIA)
RTL Design
RTL Verilog Clock Design Micro-architecture SoC
Senior ASIC Engineer — PMU, Datacenter & AI SoCs (NVIDIA)
AI Silicon
RTL Coding Architecture Power Management ASIC AI Silicon
FPGA IP Software Development Engineer (Altera)
FPGA
FPGA VLSI Embedded Systems IP Development
Verification Intern (AST SpaceMobile)
✅ Fresher FriendlyVerification
SystemVerilog Design Verification Digital Logic
Graduate Engineer Trainee (GET) — Electronics & Embedded Systems (Quest Global)
✅ Fresher FriendlySoC Architecture
Electronics Fundamentals Embedded Systems VLSI Basics
Intern - HW (Silicon Labs)
✅ Fresher FriendlyDFT
Hardware Design Digital Electronics Schematic Capture
ASIC Engineer — RTL Design Quality, CDC/RDC (NVIDIA)
AI Silicon
Verilog CDC RDC Netlist QC RTL Methodology
Senior ASIC Design Engineer — DFX (NVIDIA)
SoC Architecture
SoC Architecture RTL Design Verilog Micro-architecture
Senior VLSI Design/Verification Engineer (BigEndian Semiconductors)
Verification
RTL Design SystemVerilog UVM SoC Verification
Senior FPGA Design & Verification Engineer (Qubist Solutions)
FPGA
FPGA VHDL Verilog Embedded Systems Verification
Design Verification Engineer (HCLTech)
Verification
SystemVerilog UVM ASIC/SoC Verification
IP Physical Design Engineer (Marvell Technology)
Physical Design
Physical Design PnR STA ICC2/Innovus
SoC Audio Engineer, Platform Architecture (Apple)
SoC Architecture
SoC Architecture Audio Processing System Design C/C++
CPU Firmware Verification and Validation Engineer (Qualcomm)
Verification
CPU Verification Firmware SystemVerilog UVM Debug
Interim Engineering Intern — Systems 2026 (Qualcomm)
✅ Fresher FriendlySoC Architecture
Systems Engineering C/C++ Embedded Software SoC Basics
Staff R&D Software Engineer — DFT (Synopsys)
EDA Tools
DFT C/C++ Data Structures EDA Software Development
Principal Product Engineering (Cadence)
EDA Tools
EDA Tools Product Engineering Customer Support Scripting
Physical Design Engineer (SignOff Semiconductors)
Physical Design
Physical Design Cadence Innovus Synthesis STA PnR
DFT Engineer (7Rays Semiconductors)
DFT
BSCAN MBIST SCAN DFT Insertion ATPG
Optical Engineer — 0–2 Years (Azista Space)
✅ Fresher FriendlyPhotonics
Optical Engineering Applied Optics Photonics Electro-optical Systems
ASIC Hardware Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
Verilog RTL Design Microarchitecture Digital Logic Design
Senior ASIC Physical Design Engineer, Netlisting (NVIDIA)
Physical Design
Physical Design Floorplan Timing Closure PnR GDSII
Physical Design Engineer — Intern (EdgeSilica)
✅ Fresher FriendlyPhysical Design
Floorplanning Placement Clock Tree Synthesis Physical Design
VLSI / Semiconductor Engineer — Entry-Level (Akademika Lab Solutions)
✅ Fresher FriendlyDFT
VLSI Fundamentals Digital Electronics Lab Equipment Design
Senior ASIC Design Engineer – Clocks IP (NVIDIA)
SoC Architecture
Clock Architecture GPU/CPU Clocking Circuit Design Timing
SoC Pre-Silicon Engineering Program Manager (Apple)
SoC Architecture
SoC/VLSI Chip Design ASIC Chip Design Program Management
Senior VLSI Design Engineer — IO Design, High Speed DDR (Sandisk)
RTL Design
IO Design High Speed DDR Circuit Design VLSI
Wireless R&D IP Verification Sr Engineer (Qualcomm)
Verification
IP Verification FPGA DSP Systems SystemVerilog UVM
CPU STA CAD Engineer (Lead/Staff/Sr Staff) (Qualcomm)
EDA Tools
Static Timing Analysis CAD Tools CPU Design EDA Scripting
Intern, Design Validation (Silicon Labs)
✅ Fresher FriendlyDFT
Design Validation Semiconductor Test Digital Electronics
ASIC Design Engineer, BOOT and Power Management — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
RTL Design Verilog Power Management Automotive SoC
ASIC Design Engineer, High Speed IO (NVIDIA)
RTL Design
RTL Design UFS Ethernet PCIe USB IP
Memory CAD Software Engineer (Qualcomm)
EDA Tools
Memory Compiler CAD Flows Circuit Design Digital/Analog
VLSI ODC Team — Campus 2026 (FiveForce Technologies)
✅ Fresher FriendlyRTL Design
Verilog Digital Design RTL Basics Computer Architecture
DFT DV Engineer (QTIMINDS)
DFT
DFX Verification Scan ATPG SystemVerilog UVM
Senior DFT Engineer (Mirafra Technologies)
DFT
DFT Scan Insertion ATPG MBIST SoC Test
R&D FPGA Engineering Intern (Keysight Technologies)
✅ Fresher FriendlyFPGA
FPGA VHDL/Verilog Signal Processing Lab Instrumentation
ASIC Physical Design Engineer, Netlisting — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
Physical Design Synthesis STA Place & Route Netlist QC
Senior ASIC Design Verification Infrastructure and Tools Engineer — GPU (NVIDIA)
Verification
SystemVerilog UVM RTL Compose CI/CD Automation Python
SoC Audio Engineer, Platform Architecture (Apple)
SoC Architecture
SoC Architecture DSP Audio Subsystem Signal Processing
Senior Standard Cell and IP Application Engineer (Intel)
EDA Tools
Standard Cell Design IP Characterization Foundry Enablement EDA Tools
Engineer — 0-2 Years Experience (Qualcomm)
✅ Fresher FriendlyRTL Design
C/C++ Software Feature Development Digital Design Basics
DFT Design Engineer (AMD)
DFT
DFT Scan Insertion ATPG BIST VLSI Test Architecture
SoC Physical Design Engineer, PnR (Apple)
Physical Design
Physical Implementation Netlist to Tapeout Place and Route STA
DFT Engineer (Qualcomm)
DFT
DFT Implementation Team Leadership Scan ATPG BIST
Senior Design Verification Engineer (Excel VLSI Technologies)
Verification
ASIC/IP/SoC Verification SystemVerilog UVM Formal Verification
VLSI Design Verification Engineer — Fresher (Multiple Companies via LinkedIn)
✅ Fresher FriendlyVerification
Verilog SystemVerilog Digital Electronics RTL Basics
VLSI RTL Design / FPGA Prototyping Intern (Multiple Companies via LinkedIn)
✅ Fresher FriendlyRTL Design
Verilog Xilinx FPGA Synthesis RTL Coding
VLSI Physical Design Engineer — Fresher (Multiple Companies via LinkedIn)
✅ Fresher FriendlyPhysical Design
Floorplanning CTS Timing Closure Physical Verification
Senior ASIC Design Engineer — Agentic AI (NVIDIA)
AI Silicon
Verilog Micro-architecture RTL Development AI Accelerators
ASIC Physical Design Engineer (NVIDIA)
Physical Design
Synthesis Floorplanning Formal Check GDSII Timing Closure
Senior Verification Engineer — ARM Fabric Unit Level (NVIDIA)
Verification
ARM Architecture SystemVerilog UVM Protocol Verification
VLSI Trained Fresher — Design Engineer (Vaaluka Solutions)
✅ Fresher FriendlyRTL Design
Verilog VLSI Fundamentals Digital Design Basic RTL
Design Verification Engineer (TYLsemi)
Verification
SystemVerilog UVM Testbench Architecture IP/SoC Verification
Principal ASIC Power Engineer — AI Inference Silicon (Positron AI)
AI Silicon
ASIC Power Architecture Low Power Design AI Accelerators Power Analysis
Hardware System Validation Engineer (Apple)
SoC Architecture
SoC Bring-up System Validation Power & Performance Analysis Lab Automation
Senior Silicon Photonics Design Engineer (Intel)
Photonics
Silicon Photonics Photonic Integrated Circuits Optical Design Simulation Tools
3D-IC Application Engineer (Siemens EDA)
EDA Tools
3D-IC Design EDA Tools Calibre Innovator3D IC Integrator
Physical Design Engineer — 0-2 Years Experience (Quess Corp)
✅ Fresher FriendlyPhysical Design
Floorplanning Placement Clock Tree Synthesis Routing Timing Closure
Semiconductor Design Intern (Collins Aerospace India)
✅ Fresher FriendlyRTL Design
Verilog RTL Design Digital Design Fundamentals Semiconductor Basics
Senior ASIC Physical Design Engineer, Netlisting (NVIDIA)
Physical Design
Netlist Synthesis Static Timing Analysis Physical Design Python Formal Verification
DFT-ATPG Engineer (AMD)
DFT
ATPG Scan Insertion DFT Architecture Mentor Tessent
ASIC Physical Design Engineer (NVIDIA)
Physical Design
Static Timing Analysis Synthesis Formal Verification Python/Perl/TCL Synopsys/Cadence EDA
Senior VLSI Design Engineer — IO Design, High Speed DDR (SanDisk)
RTL Design
IO Circuit Design DDR4 DDR5 LPDDR4 LPDDR5 Memory Interfaces
Associate Engineer, System Design Engineering — FPGA Design (SanDisk)
FPGA
FPGA Design RTL Development Embedded Systems Digital Design
VLSI Engineer L3 (Wipro)
DFT
VLSI Design Verilog EDA Tools Semiconductor Systems DFT
Senior VLSI Design/Verification Engineer (BigEndian Semiconductors)
Verification
VLSI Design Verification SystemVerilog UVM ASIC Design
IP/SoC Design — Engineer (Qualcomm)
SoC Architecture
IP Design SoC Architecture Verilog RTL Chip Integration
ASIC Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyRTL Design
RTL Design Verilog ASIC Design Flow Logic Synthesis Timing Analysis
ASIC Clocks Design Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyPhysical Design
RTL Design Verilog Clock Design Logic Synthesis Perl/Python Scripting
Equipment Engineer Trainee — Semicon Manufacturing Fab (MEL Systems and Services Ltd)
✅ Fresher FriendlyPackaging
Semiconductor Manufacturing Equipment Maintenance Fab Operations Packaging
Mixed Signal Design Verification Engineer (Intel)
Verification
Mixed Signal Verification SystemVerilog UVM Analog/Digital Co-Simulation
VLSI / Semiconductor Engineer — Entry Level (Akademika Lab Solutions)
✅ Fresher FriendlyRTL Design
RTL Coding Verilog Digital/Analog VLSI Design Simulation
CPU Circuit Design Lead (Intel)
SoC Architecture
CPU Circuit Design Microarchitecture Custom Design Timing Closure
Senior Standard Cell and IP Application Engineer (Intel)
EDA Tools
Standard Cell Libraries IP Enablement Foundry Customer Engineering Liberty/LEF
DFT-DV Engineer (AMD)
DFT
DFT ATPG Scan Insertion BIST Design Verification
Senior FPGA Engineer (VySystems)
FPGA
FPGA VHDL Verilog Defense/Aerospace Electronics Xilinx/Altera Tools
Sr. Silicon Photonics Design Engineer (Nokia)
Photonics
Silicon Photonics PIC Design Optical Interconnect Simulation
Advanced Packaging / Flip Chip Engineer (Onyx)
Packaging
Flip Chip Packaging Advanced Packaging Silicon Photonics Integration Reliability
ASIC Verification Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyVerification
SystemVerilog UVM RTL Verification Coverage Python
Early Careers SoC Physical Design Engineer (Apple)
✅ Fresher FriendlyPhysical Design
Physical Design PnR Floorplanning STA Clock/Power Distribution
Off Campus Drive — Engineer, Fresher (Micron Technology)
✅ Fresher FriendlyAI Silicon
Digital Design Verilog Memory Architecture C/C++
Off Campus Recruitment Intern — Technical Engineering (Synopsys)
✅ Fresher FriendlyEDA Tools
EDA Tools Semiconductor Fundamentals Scripting Digital Design Basics
Senior Engineer, Design Verification — Entry Level (Marvell)
✅ Fresher FriendlyVerification
SystemVerilog UVM Design Verification Digital Logic
Lead Digital Design and Verification for Mixed-Signal IP/Subsystem (NXP Semiconductors)
RTL Design
Digital Design Mixed-Signal Verification RTL SystemVerilog IP Integration
Staff, VLSI Design Engineering — Verification, NAND Memory (SanDisk)
Verification
SystemVerilog UVM NAND Memory Design Verification
Package Design Engineer (Broadcom)
Packaging
IC Package Design Flip-Chip BGA High-Speed ASIC Packaging Signal Integrity
VLSI Design Engineer — Entry Level (SiliconBoard)
✅ Fresher FriendlyRTL Design
Digital Design Analog Design Physical Design Verilog VLSI Fundamentals
SoC Architect / uArchitect (Qualcomm)
✅ Fresher FriendlySoC Architecture
SoC Architecture Microarchitecture Performance Modeling ARM Architecture
Staff Engineer, Physical Design (Marvell)
Physical Design
Physical Design Floorplanning Place and Route STA Methodology Development
IC Packaging Engineer — WLP (Apple)
Packaging
IC Packaging Wafer-Level Packaging Package Concept Exploration Materials Selection
PCB Design EDA and AI Engineer — New College Grad 2026 (NVIDIA)
✅ Fresher FriendlyEDA Tools
PCB Design EDA Automation Python Machine Learning Hardware Design
SoC Architect — AI Startup (via Acceler8 Talent)
SoC Architecture
SoC Architecture Full-Chip Design AI Accelerator Platforms Power/Performance Tradeoffs
Physical Design Methodology Engineer, AI HW IP (Tenstorrent)
Physical Design
Physical Design PnR Methodology Synthesis Timing Closure AI HW IP
DFT Engineer — Entry Level (VEDAMSEMI)
✅ Fresher FriendlyDFT
DFT SCAN ATPG BIST Design-for-Test Architecture
RTL Design Engineer, CPU (Intel)
RTL Design
RTL Coding SystemVerilog Logic Design Simulation CPU Microarchitecture
Staff Engineer, Post-Silicon Validation — AI-Enabled Workflows (Analog Devices)
Verification
Post-Silicon Validation ASIC Test Characterization AI-Enabled Test Automation
Junior FPGA Design Engineer / Intern (Tannera)
✅ Fresher FriendlyFPGA
FPGA Design VHDL Verilog PHY Development Digital Signal Processing
Senior Principal Optoelectronics Engineer — Silicon Photonics (Coherent Corp)
Photonics
Silicon Photonics Optoelectronics Modeling Semiconductor Lasers Photonic IC Design
New College Grad — EDA/CAD Engineer (Micron Technology)
✅ Fresher FriendlyEDA Tools
EDA/CAD Tools AI/ML Automation Python Design Flow Qualification
Packaging Integration Engineer — 2026 New College Graduate (GlobalFoundries)
✅ Fresher FriendlyPackaging
Package Integration Process Development Reliability Characterization Data Analysis
Staff Design Verification Engineer, AI HW (Tenstorrent)
AI Silicon
SystemVerilog UVM AI Accelerator Verification RISC-V Python