The weekly newsletter for VLSI and AI-chip engineers. Signals, jobs, tools, and deep-dives — curated so you don’t have to be on Twitter at midnight.
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One major development from the semiconductor + AI space, with the context that actually matters to a working engineer.
New EDA releases, open-source verification tools, and research papers pulled from DAC, ICCAD, and arXiv — summarised in two sentences.
Hand-picked VLSI and AI-hardware roles from Intel, Qualcomm, Synopsys, and high-growth startups. Fresher-friendly roles flagged separately.
One long-form technical piece per issue, written at senior-engineer level. UVM patterns, formal methods, AI-assisted verification, floorplan trade-offs.
The most interesting discussion from our 20,000+ Telegram community that week, surfaced with context for readers who missed it.
Semiconductor startups funded, acquired, or IPO-bound. Know the landscape before your next interview or your next career move.
Intel’s 18A comeback, Synopsys VSO platform, chiplet standardisation, and why every SoC team is now hiring an AI engineer.
How LLMs are changing the EDA landscape and what verification engineers need to know about the shift.
Property checking, assertion libraries, and where formal fits inside a modern tapeout schedule.
No filler, no sponsored posts you didn’t ask for. The list is ours. When tools get built, subscribers hear about them first.
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Weekly intelligence on VLSI, AI for EDA, and chip careers. 20,000+ engineers already inside.