The Physical Design Journey
Physical Design (PD) is the process of transforming a verified RTL netlist into a manufacturable GDSII layout. It’s where timing, power, and area constraints become real geometric realities. Here’s the complete flow every PD engineer must master.
Step 1: Synthesis
The RTL (Verilog/VHDL) is synthesized into a gate-level netlist using tools like Synopsys Design Compiler or Cadence Genus. Constraints (.sdc file) guide timing optimization. Output: gate-level netlist + timing reports.
Step 2: Floorplanning
Define the die area, place hard macros (SRAMs, IPs), establish power grid structure, and define the IO ring. This is the most critical step — poor floorplanning causes downstream problems that are very costly to fix.
Step 3: Power Planning
Create the power distribution network (PDN): power rings around the core, power stripes across the chip, and standard cell rails. Analyze and fix IR drop and electromigration (EM) violations.
Step 4: Placement
Standard cells are placed within the core area. Modern placers (Cadence Innovus, Synopsys ICC2) optimize for timing, congestion, and power simultaneously using ML-based algorithms.
Step 5: Clock Tree Synthesis (CTS)
Build the clock distribution tree to minimize skew and latency across all flip-flops. Key metrics: skew, insertion delay, slew. Use H-tree or mesh topologies for high-performance designs.
Step 6: Routing
Connect all cells using metal layers. Global routing assigns nets to routing tracks; detailed routing fills in actual metal shapes. Design Rule Check (DRC) violations must be zero at signoff.
Step 7: Signoff
STA (Static Timing Analysis), IR drop analysis, DRC/LVS checks, and parasitic extraction. Tools: Synopsys PrimeTime, Cadence Voltus, Mentor Calibre.
Learn Physical Design
Watch our complete PD tutorial series on the VLSIChaps YouTube channel and discuss with experts in our Telegram community.