Ace Your VLSI Interview
Whether you’re interviewing at Intel, Qualcomm, Apple Silicon, NVIDIA, or an EDA startup, these are the questions you must be ready for. We’ve curated the most commonly asked questions with detailed answers.
Digital Design Questions
1. What is setup time and hold time?
Setup time is the minimum time data must be stable before the clock edge. Hold time is the minimum time data must remain stable after the clock edge. Violations cause metastability — the flip-flop enters an unpredictable state.
2. Explain clock domain crossing (CDC) and how to handle it
CDC occurs when signals cross between logic operating in different clock domains. Solutions include synchronizers (2FF sync for single-bit), handshaking protocols, and FIFOs for multi-bit data. Always use dedicated CDC analysis tools like Cadence Jasper CDC or Synopsys SpyGlass.
3. What is the difference between a latch and a flip-flop?
A latch is level-sensitive (transparent when enable is high). A flip-flop is edge-triggered. Latches are power-efficient but harder to time; flip-flops are standard in synchronous design.
Verification Questions
4. What are the phases in UVM?
Build, Connect, Start of Elaboration, End of Elaboration, Start of Simulation, then run phases: Reset, Configure, Main, Shutdown — all derived from uvm_phase. Post-simulation: Extract, Check, Report, Final.
5. What is functional coverage vs code coverage?
Code coverage measures which lines/branches/conditions of RTL were exercised. Functional coverage measures whether design-intent scenarios were verified — it’s designer-defined and more meaningful for sign-off.
Physical Design Questions
6. What is IR drop and how do you fix it?
IR drop is voltage drop across the power grid resistance (V = I×R), causing cells to operate at lower voltage and potentially violate timing. Fixes: add decaps, widen power straps, add power rails, rebalance the power grid.
7. Explain floorplanning objectives
Define chip area, place macros (memories, IPs), create power grid, define IO pad ring, and establish partition boundaries. Good floorplanning directly impacts final PPA (Power, Performance, Area).
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