The basic requirement from the counter operation is incrementing or decrementing the values with the occurrence of a clock edge. This behavior of sequential design operation is possible with Flip Flops, which toggles to make the three or four-digit binary number.
Other Flip Flops like D Flip Flops, and SR Flip Flops, are not the candidate as D is a transparent Flip Flops and SR has invalid output with 1 1 inputs.
T Flip Flop or JK Flip Flops are the correct options.
Important thing for using a counter is it has a toggle Condition when J and K are both made high at the clock edge then the output will also toggle from one state to the other.
Basically, the JK Flip Flop is derived or constructed from SR Flip Flop including by adding the Clock Input Circuit that Prevents incorrect output conditions when S and R will overcome the Problem JK Flip Flop is been Used.
Fig. 1 shows the Flip As shown in the waveform, with each positive-going clock edge the Flip Flop output Q0 toggles, which goes as a clock to the next flip flop clock and then Q1 toggles via Q0bar. And so on.
Fig. 2 below shows the JK Flip Flop gate level implementation of JK Flip Flop.
Fig. 3 is the truth table of JK Flip Flop.
Thus the characteristics and expectations are as per requirements. Thus it becomes most suitable candidate.
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